AM3874 datasheet(320/361 Pages) TI

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MCB_CLK

MCB_FS

MCB_DX

MCB_DR

MCB_DX7

MCB_DX6

MCB_DX0

MCB_DR7

MCB_DR6

MCB_DR0

AM3874, AM3871

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

www.ti.com

The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive

output data and capture input data.

MCBSP_CLK corresponds to either MCBSP_CLKX or MCBSP_CLKR; MCBSP_FS corresponds to either

MCBSP_FSX

MCBSP_FSR.

McBSP

6-pin

mode:

and

data

pins;

CLKX,

CLKR,

FSX

and

FSR

control

pins.

McBSP in 4-pin mode: DX and DR as data pins; CLKX and FSX pins as control pins. The CLKX and FSX pins are

internally looped back via software configuration, respectively to the CLKR and FSR internal signals for data receive.

The polarity of McBSP frame synchronization is software configurable.

The active clock edge selection of MCBSP_CLK (rising or falling) on which MCBSP_DX data is latched and

MCBSP_DR data is sampled is software configurable.

Timing diagrams are for data delay set to 1.

For further details about the registers used to configure McBSP, see the Multichannel Buffered Serial Port (McBSP)

chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (Literature Number: SPRUGZ7).

Figure 8-83. McBSP Master Mode Timing

Table 8-83. Timing Requirements for McBSP - Slave Mode(1)

(see Figure 8-84)

OPP100/120/166

NO.

UNIT

MIN

MAX

tc(CLK)

Cycle time, MCB_CLK period(2)

20.83

tw(CLKL)

Pulse duration, MCB_CLK low(2)

0.5*P - 1(3)

tw(CLKH)

Pulse duration, MCB_CLK high(2)

0.5*P - 1(3)

tsu(FSV-CLKAE)

Setup time, MCB_FS valid before MCB_CLK active edge(2)(4)

3.8

th(CLKAE-FSV)

Hold time, MCB_FS valid after MCB_CLK active edge(2)(4)

0.5

tsu(DRV-CLKAE)

Setup time, MCB_DR valid before MCB_CLK active edge (2)

3.8

th(CLKAE-DRV)

Hold time, MCB_DR valid after MCB_CLK active edge(2)

0.5

(1)

The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive output data and capture

input data.

(2)

MCB_CLK corresponds to either MCB_CLKX or MCB_CLKR.

(3)

P = MCB_CLKX/MCB_CLKR output CLK period, in ns; use whichever value is greater. This parameter applies to the maximum McBSP

frequency. Operate serial clocks (CLKX/R) in the reasonable range of 40/60 duty cycle.

(4)

MCB_FS corresponds to either MCB_FSX or MCB_FSR.

Table 8-84. Switching Characteristics Over Recommended Operating Conditions for McBSP - Slave

Mode(1)

(see Figure 8-84)

OPP100/120/166

NO.

PARAMETER

UNIT

MIN

MAX

td(CLKXAE-DXV)

Delay time, input MCB_CLKx active edge to output MCB_DX valid

0.5

12.5

(1)

The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive output data and capture

input data.

320

Peripheral Information and Timings

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