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AM3874 Datasheet(PDF) 322 Page - Texas Instruments |
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AM3874 Datasheet(HTML) 322 Page - Texas Instruments |
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322 / 361 page  AM3874, AM3871 SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com 8.16 MultiMedia Card/Secure Digital/Secure Digital Input Output (MMC/SD/SDIO) The device includes 3 MMC/SD/SDIO Controllers which are compliant with MMC V4.3, Secure Digital Part 1 Physical Layer Specification V2.00 and Secure Digital Input Output (SDIO) V2.00 specifications. The device MMC/SD/SDIO Controller has the following features: • MultiMedia card (MMC) • Secure Digital (SD) memory card • MMC/SD protocol support • SDIO protocol support • Programmable clock frequency • 1024 byte read/write FIFO to lower system overhead • Slave EDMA transfer capability • SD High capacity support 8.16.1 MMC/SD/SDIO Peripheral Register Descriptions Table 8-85. MMC/SD/SDIO Registers(1) MMC/SD/SDIO0 MMC/SD/SDIO1 MMC/SD/SDIO2 ACRONYM REGISTER NAME HEX ADDRESS HEX ADDRESS HEX ADDRESS 0x4806 0000 0x481D 8000 0x4781 0000 MMCHS_HL_REV IP Revision Identifier 0x4806 0004 0x481D 8004 0x4781 0004 MMCHS_HL_HWINF Hardware Configuration O 0x4806 0010 0x481D 8010 0x4781 0010 MMCHS_HL_SYSCO Clock Management Configuration NFIG 0x4806 0110 0x481D 8110 0x4781 0110 MMCHS_SYSCONFI System Configuration G 0x4806 0114 0x481D 8114 0x4781 0114 MMCHS_SYSSTATU System Status S 0x4806 0124 0x481D 8124 0x4781 0124 MMCHS_CSRE Card status response error 0x4806 0128 0x481D 8128 0x4781 0128 MMCHS_SYSTEST System Test 0x4806 012C 0x481D 812C 0x4781 012C MMCHS_CON Configuration 0x4806 0130 0x481D 8130 0x4781 0130 MMCHS_PWCNT Power counter 0x4806 0200 0x481D 8200 0x4781 0200 MMCHS_SDMASA SDMA System address: 0x4806 0204 0x481D 8204 0x4781 0204 MMCHS_BLK Transfer Length Configuration 0x4806 0208 0x481D 8208 0x4781 0208 MMCHS_ARG Command argument 0x4806 020C 0x481D 820C 0x4781 020C MMCHS_CMD Command and transfer mode 0x4806 0210 0x481D 8210 0x4781 0210 MMCHS_RSP10 Command Response 0 and 1 0x4806 0214 0x481D 8214 0x4781 0214 MMCHS_RSP32 Command Response 2 and 3 0x4806 0218 0x481D 8218 0x4781 0218 MMCHS_RSP54 Command Response 4 and 5 0x4806 021C 0x481D 821C 0x4781 021C MMCHS_RSP76 Command Response 6 and 7 0x4806 0220 0x481D 8220 0x4781 0220 MMCHS_DATA Data 0x4806 0224 0x481D 8224 0x4781 0224 MMCHS_PSTATE Present state 0x4806 0228 0x481D 8228 0x4781 0228 MMCHS_HCTL Host Control 0x4806 022C 0x481D 822C 0x4781 022C MMCHS_SYSCTL SD system control 0x4806 0230 0x481D 8230 0x4781 0230 MMCHS_STAT Interrupt status 0x4806 0234 0x481D 8234 0x4781 0234 MMCHS_IE Interrupt SD enable 0x4806 0238 0x481D 8238 0x4781 0238 MMCHS_ISE Interrupt Signal Enable 0x4806 023C 0x481D 823C 0x4781 023C MMCHS_AC12 Auto CMD12 Error Status 0x4806 0240 0x481D 8240 0x4781 0240 MMCHS_CAPA Capabilities 0x4806 0248 0x481D 8248 0x4781 0248 MMCHS_CUR_CAPA Maximum current capabilities (1) SD/SDIO registers are limited to 32-bit data accesses; 16-bit and 8-bit accesses are not allowed and can corrupt register content. 322 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM3874 AM3871 |
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