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AM3874 Datasheet(PDF) 326 Page - Texas Instruments

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Part # AM3874
Description  AM387x Sitara??ARM Processors
PDF  361 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3874 Datasheet(HTML) 326 Page - Texas Instruments

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AM3874, AM3871
SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013
www.ti.com
Table 8-88. PCIe Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
0x5100 0074
GPR1
General Purpose 1
0x5100 0078
GPR2
General Purpose 2
0x5100 007C
GPR3
General Purpose 3
0x5100 0100
MSI0_IRQ_STATUS_RAW
MSI 0 Interrupt Raw Status
0x5100 0104
MSI0_IRQ_STATUS
MSI 0 Interrupt Enabled Status
0x5100 0108
MSI0_IRQ_ENABLE_SET
MSI 0 Interrupt Enable Set
0x5100 010C
MSI0_IRQ_ENABLE_CLR
MSI 0 Interrupt Enable Clear
0x5100 0180
IRQ_STATUS_RAW
Raw Interrupt Status
0x5100 0184
IRQ_STATUS
Interrupt Enabled Status
0x5100 0188
IRQ_ENABLE_SET
Interrupt Enable Set
0x5100 018C
IRQ_ENABLE_CLR
Interrupt Enable Clear
0x5100 01C0
ERR_IRQ_STATUS_RAW
Raw ERR Interrupt Status
0x5100 01C4
ERR_IRQ_STATUS
ERR Interrupt Enabled Status
0x5100 01C8
ERR_IRQ_ENABLE_SET
ERR Interrupt Enable Set
0x5100 01CC
ERR_IRQ_ENABLE_CLR
ERR Interrupt Enable Clear
0x5100 01D0
PMRST_IRQ_STATUS_RAW
Power Management and Reset Interrupt Status
0x5100 01D4
PMRST_IRQ_STATUS
Power Management and Reset Interrupt Enabled Status
0x5100 01D8
PMRST_ENABLE_SET
Power Management and Reset Interrupt Enable Set
0x5100 01DC
PMRST_ENABLE_CLR
Power Management and Reset Interrupt Enable Clear
0x5100 0200
OB_OFFSET_INDEXn
Outbound Translation Region N Offset Low and Index
0x5100 0204
OB_OFFSETn_HI
Outbound Translation Region N Offset High
0x5100 0300
IB_BAR0
Inbound Translation Bar Match 0
0x5100 0304
IB_START0_LO
Inbound Translation 0 Start Address Low
0x5100 0308
IB_START0_HI
Inbound Translation 0 Start Address High
0x5100 030C
IB_OFFSET0
Inbound Translation 0 Address Offset
0x5100 0310
IB_BAR1
Inbound Translation Bar Match 1
0x5100 0314
IB_START1_LO
Inbound Translation 1 Start Address Low
0x5100 0318
IB_START1_HI
Inbound Translation 1 Start Address High
0x5100 031C
IB_OFFSET1
Inbound Translation 1 Address Offset
0x5100 0320
IB_BAR2
Inbound Translation Bar Match 2
0x5100 0324
IB_START2_LO
Inbound Translation 2 Start Address Low
0x5100 0328
IB_START2_HI
Inbound Translation 2 Start Address High
0x5100 032C
IB_OFFSET2
Inbound Translation 2 Address Offset
0x5100 0330
IB_BAR3
Inbound Translation Bar Match 3
0x5100 0334
IB_START3_LO
Inbound Translation 3 Start Address Low
0x5100 0338
IB_START3_HI
Inbound Translation 3 Start Address High
0x5100 033C
IB_OFFSET3
Inbound Translation 3 Address Offset
0x5100 0380
PCS_CFG0
PCS Configuration 0
0x5100 0384
PCS_CFG1
PCS Configuration 1
0x5100 0388
PCS_STATUS
PCS Status
0x5100 038C
SERDES_STATUS
SerDes Status
0x5100 0390
SERDES_RXCFG0
SerDes Receive Configuration 0 Register
0x5100 0394
SERDES_RXCFG1
SerDes Receive Configuration 1 Register
0x5100 0398
SERDES_RXCFG2
SerDes Receive Configuration 2 Register
0x5100 039C
SERDES_RXCFG3
SerDes Receive Configuration 3 Register
0x5100 03A0
SERDES_RXCFG4
SerDes Receive Configuration 4 Register
0x5100 03A4
SERDES_TXCFG0
SerDes Transmit Configuration 0 Register
326
Peripheral Information and Timings
Copyright © 2011–2013, Texas Instruments Incorporated
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