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AM3874 Datasheet(PDF) 329 Page - Texas Instruments |
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AM3874 Datasheet(HTML) 329 Page - Texas Instruments |
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329 / 361 page  AM3874, AM3871 www.ti.com SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013 Table 8-94. PCI Express Extended Capabilities Register Summary (continued) HEX ADDRESS ACRONYM NAME 5100_1110 PCIE_CERR PCI Express Correctable Error Status Register 5100_1114 PCIE_CERR_MASK PCI Express Correctable Error Mask Register 5100_1118 PCIE_ACCR PCI Express Advanced Capabilities and Control Register 5100_111C HDR_LOG0 Header Log 0 Register 5100_1120 HDR_LOG1 Header Log 1 Register 5100_1124 HDR_LOG2 Header Log 2 Register 5100_1128 HDR_LOG3 Header Log 3 Register 5100_112C RC_ERR_CMD Root Error Command Register 5100_1130 RC_ERR_ST Root Error Status Register 5100_1134 ERR_SRC_ID Error Source Identification Register Table 8-95. Port Logic Register Summary HEX ADDRESS ACRONYM NAME 5100_1700 PL_ACKTIMER Ack Latency Time and Replay Timer Register 5100_1704 PL_OMSG Other Message Register 5100_1708 PL_FORCE_LINK Port Force Link Register 5100_170C ACK_FREQ Ack Frequency Register 5100_1710 PL_LINK_CTRL Port Link Control Register 5100_1714 LANE_SKEW Lane Skew Register 5100_1718 SYM_NUM Symbol Number Register 5100_171C SYMTIMER_FLTMASK Symbol Timer and Filter Mask Register 5100_1720 FLT_MASK2 Filter Mask 2 Register 5100_1728 DEBUG0 Debug 0 Register 5100_172C DEBUG1 Debug 1 Register 5100_180C PL_GEN2 Gen2 Register 8.17.2 PCIe Electrical Data/Timing Texas Instruments (TI) has performed the simulation and system characterization to ensure that the PCIe peripheral meets all AC timing specifications as required by the PCI Express Base 2.0 Specification. Therefore, the AC timing specifications are not reproduced here. For more information on the AC timing specifications, see Sections 4.3.3.5 and 4.3.4.4 of the PCI Express Base 2.0 Specification. 8.17.3 PCIe Design and Layout Guidelines 8.17.3.1 Clock Source A standard 100-MHz PCIe differential clock source must be used for PCIe operation (for more details, see Section 7.4.2, SERDES CLKN/P Input Clock). 8.17.3.2 PCIe Connections and Interface Compliance The PCIe interface on the device is compliant with the PCI Express Base 2.0 Specification. Refer to the PCIe specifications for all connections that are described in it. For coupling capacitor selection, see Section 8.17.3.2.1, Coupling Capacitors. The use of PCIe-compatible bridges and switches is allowed for interfacing with more than one other processor or PCIe device. Copyright © 2011–2013, Texas Instruments Incorporated Peripheral Information and Timings 329 Submit Documentation Feedback Product Folder Links: AM3874 AM3871 |
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