AM3874 datasheet(321/361 Pages) TI

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MCB_CLK

MCB_FS

MCB_DX

MCB_DR

MCB_DX7

MCB_DX6

MCB_DX0

MCB_DR7

MCB_DR6

MCB_DR0

AM3874, AM3871

www.ti.com

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive

output data and capture input data.

MCBSP_CLK corresponds to either MCBSP_CLKX or MCBSP_CLKR; MCBSP_FS corresponds to either

MCBSP_FSX

MCBSP_FSR.

McBSP

6-pin

mode:

and

data

pins;

CLKX,

CLKR,

FSX

and

FSR

control

pins.

McBSP in 4-pin mode: DX and DR as data pins; CLKX and FSX pins as control pins. The CLKX and FSX pins are

internally looped back via software configuration, respectively to the CLKR and FSR internal signals for data receive.

The polarity of McBSP frame synchronization is software configurable.

The active clock edge selection of MCBSP_CLK (rising or falling) on which MCBSP_DX data is latched and

MCBSP_DR data is sampled is software configurable.

Timing diagrams are for data delay set to 1.

For further details about the registers used to configure McBSP, see the Multichannel Buffered Serial Port (McBSP)

chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (Literature Number: SPRUGZ7).

Figure 8-84. McBSP Slave Mode Timing

Peripheral Information and Timings

321

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