Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

AM3874 Datasheet(PDF) 340 Page - Texas Instruments

Click here to check the latest version.
Part # AM3874
Description  AM387x Sitara??ARM Processors
PDF  361 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3874 Datasheet(HTML) 340 Page - Texas Instruments

Back Button AM3874 Datasheet HTML 336Page - Texas Instruments AM3874 Datasheet HTML 337Page - Texas Instruments AM3874 Datasheet HTML 338Page - Texas Instruments AM3874 Datasheet HTML 339Page - Texas Instruments AM3874 Datasheet HTML 340Page - Texas Instruments AM3874 Datasheet HTML 341Page - Texas Instruments AM3874 Datasheet HTML 342Page - Texas Instruments AM3874 Datasheet HTML 343Page - Texas Instruments AM3874 Datasheet HTML 344Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 340 / 361 page
background image
SPI_SCS[x] (Out)
SPI_SCLK (Out)
SPI_SCLK (Out)
SPI_D[x] (In)
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=0
EPOL=1
POL=0
POL=1
8
9
3
4
2
1
2
3
5
SPI_SCS[x] (Out)
SPI_SCLK (Out)
SPI_SCLK (Out)
SPI_D[x] (In)
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
PHA=1
EPOL=1
POL=0
POL=1
8
9
3
2
1
2
3
1
4
5
4
5
5
4
1
AM3874, AM3871
SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013
www.ti.com
Figure 8-91. SPI Master Mode Receive Timing
Table 8-106. Timing Requirements for SPI - Slave Mode
(see Figure 8-92 and Figure 8-93)
OPP100/120/166
NO.
UNIT
MIN
MAX
1
tc(SPICLK)
Cycle time, SPI_CLK(1)(2)
62.5(3)
ns
2
tw(SPICLKL)
Pulse duration, SPI_CLK low(1)
0.5*P - 3(4)
ns
3
tw(SPICLKH)
Pulse duration, SPI_CLK high(1)
0.5*P - 3(4)
ns
4
tsu(MOSI-SPICLK)
Setup time, SPI_D[x] valid before SPI_CLK active edge (1)
12.92
ns
5
th(SPICLK-MOSI)
Hold time, SPI_D[x] valid after SPI_CLK active edge (1)
12.92
ns
6
td(SPICLK-MISO)
Delay time, SPI_CLK active edge to SPI_D[x] transition (1)
-4.00
17.1
ns
Delay time, SPI_SCS[x] active edge to SPI_D[x]
7
td(SCS-MISO)
17.1
ns
transition(5)
8
tsu(SCS-SPICLK)
Setup time, SPI_SCS[x] valid before SPI_CLK first edge (1)
12.92
ns
(1)
This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2)
Related to the input maximum frequency supported by the SPI module.
(3)
Maximum frequency = 16 MHz
(4)
P = SPICLK period.
(5)
PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
340
Peripheral Information and Timings
Copyright © 2011–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM3874 AM3871



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com