PEB2256HT datasheet(120/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Functional Description T1/J1

Data Sheet

120

2002-08-27

5.1.3

Receive Equalization Network (T1/J1)

The FALC56 automatically recovers the signals received on pins RL1/2. The maximum

reachable length with a 22 AWG twisted-pair cable is 2000 m (~6560 ft.). After reset the

FALC56 is in short-haul mode, received signals are recovered up to -10 dB of cable

attenuation. Switching into long-haul mode is done by setting of bit LIM0.EQON = 1.

The integrated receive equalization network recovers signals with up to -36 dB of cable

attenuation in long-haul mode. Noise filters eliminate the higher frequency part of the

received signals. The incoming data is peak-detected and sliced to produce the digital

data stream. The slicing level is software selectable in four steps (45%, 50%, 55%, 67%).

The received data is then forwarded to the clock and data recovery unit.

5.1.4

Receive Line Attenuation Indication (T1/J1)

Status register RES reports the current receive line attenuation in a range from 0 to

-36 dB in 25 steps of approximately 1.4 dB each. The least significant 5 bits of this

with the most significant two bits (RES.EV1/0 = 01).

5.1.5

Receive Clock and Data Recovery (T1/J1)

The analog received signal on port RL1/2 is equalized and then peak-detected to

produce a digital signal. The digital received signal on port RDIP/N is directly forwarded

to the DPLL. The receive clock and data recovery extracts the route clock RCLK from

the data stream received at the RL1/2, RDIP/RDIN or ROID lines and converts the data

stream into a single-rail, unipolar bit stream. The clock and data recovery uses an

internally generated high frequency clock based on MCLK.

The recovered route clock or a de-jittered clock can be output on pin RCLK as shown in

Table 25.

See also Table 28 on page 126 for details of master/slave clocking.

PEB2256HT Datasheet(PDF) 120 Page - Infineon Technologies AG