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PEB2256HT Datasheet(PDF) 139 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 139 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
Functional Description T1/J1
Data Sheet
139
2002-08-27
5.2
Framer Operating Modes (T1/J1)
5.2.1
General
Activated with bit FMR1.PMOD = 1.
PCM line bit rate
:
1.544 Mbit/s
Single frame length
:
193 bit, No. 1…193
Framing frequency
:
8 kHz
Organization
:
24 time slots, No. 1…24
with 8 bits each, No. 1…8 and one preceding F-bit
Selection of one of the four permissible framing formats is performed by bits FMR4.FM1/
0. These formats are:
F4
:
4-frame multiframe
F12
:
12-frame multiframe (D4)
ESF
:
Extended Superframe (F24)
F72
:
72-frame multiframe (SLC96)
The operating mode of the FALC56 is selected by programming the carrier data rate and
characteristics, line code, multiframe structure, and signaling scheme.
The FALC56 implements all of the standard and/or common framing structures PCM24
(T1/J1, 1.544 Mbit/s) carriers. The internal HDLC controller supports all signaling
procedures including signaling frame synchronization/synthesis in all framing formats.
After reset, the FALC56 must be programmed with FMR1.PMOD = 1 to enable the T1/
J1 (PCM24) mode. Switching between the framing formats is done by bit FMR4.FM1
⁄0
for the receiver and for the transmitter.
5.2.2
General Aspects of Synchronization
Synchronization status is reported by bit FRS0.LFA (Loss Of Frame Alignment). Framing
errors (pulse frame and multiframe) are counted by the Framing Error Counter FEC.
Asynchronous state is reached if
2 out of 4 (bit FMR4.SSC1/0 = 00), or
2 out of 5 (bit FMR4.SSC1/0 = 01), or
2 out of 6 (bit FMR4.SSC1/0 = 10), or
4 consecutive multiframe pattern in ESF format are incorrect (bit FMR4.SSC1/0 = 11).
If auto mode is enabled, counting of framing errors is interrupted.
The resynchronization procedure is controlled by either one of the following procedures:
• Automatically (FMR4.AUTO = 1). Additionally, it can be triggered by the user by
setting/resetting one of the bits FMR0.FRS (force resynchronization) or FMR0.EXLS
(external loss of frame).



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