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PEB2256HT Datasheet(PDF) 254 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 254 Page - Infineon Technologies AG |
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254 / 490 page ![]() FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 254 2002-08-27 System Interface Control 1 (Read/Write) Value after reset: 00H SSC(1:0) Select System Clock SIC1.SSC(1:0) define the clocking rate on the system highway. 00 = 2.048 MHz 01 = 4.096 MHz 10 = 8.192 MHz 11 = 16.384 MHz SSD1 Select System Data Rate 1 SIC1.SSD1 and FMR1.SSD0 define the data rate on the system highway. Programming SSD1/SSD0 and corresponding data rate is shown below. 00 = 2.048 Mbit/s 01 = 4.096 Mbit/s 10 = 8.192 Mbit/s 11 = 16.384 Mbit/s RBS(1:0) Receive Buffer Size 00 = Buffer size: 2 frames 01 = Buffer size: 1 frame 10 = Buffer size: 96 bits 11 = bypass of receive elastic store BIM Bit Interleaved Mode 0 = Byte interleaved mode 1 = Bit interleaved mode XBS(1:0) Transmit Buffer Size 00 = Bypass of transmit elastic store 01 = Buffer size: 1 frame 10 = Buffer size: 2 frames 11 = Buffer size: 96 bits 70 SIC1 SSC1 SSD1 RBS1 RBS0 SSC0 BIM XBS1 XBS0 (3E) |
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