PEB2256HT datasheet(258/490 Pages) INFINEON

258 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

258

2002-08-27

Clock Mode Register 1 (Read/Write)

Value after reset: 00H

RS(1:0)

Select RCLK Source

These bits select the source of RCLK.

00 = Clock recovered from the line through the DPLL drives RCLK

01 = Clock recovered from the line through the DPLL drives RCLK

and in case of an active LOS alarm RCLK pin is set high.

10 = Clock recovered from the line is de-jittered by DCO-R to drive a

2.048 MHz clock on RCLK.

11 = Clock recovered from the line is de-jittered by DCO-R to drive a

8.192 MHz clock on RCLK.

DCS

Disable Clock-Switching

In Slave mode (LIM0.MAS = 0) the DCO-R is synchronized on the

recovered route clock. In case of loss-of-signal LOS the DCO-R

switches automatically to the clock sourced by port SYNC. Setting

this bit automatic switching from RCLK to SYNC is disabled.

STF

Select TCLK Frequency

Only applicable if the pin function TCLK port XP(A to D) is selected by

PC(4:1).XPC(3:0) = 0011

Data on XL1/2 (XDOP/N / XOID) are

clocked with TCLK.

0 =

2.048 MHz

1 =

8.192 MHz

DXJA

Disable Internal Transmit Jitter Attenuation

Setting this bit disables the transmit jitter attenuation. Reading the

data out of the transmit elastic buffer and transmitting on XL1/2

(XDOP/N/XOID) is done with the clock provided on pin TCLK. In

transmit elastic buffer bypass mode the transmit clock is taken from

SCLKX, independent of this bit.

CMR1

RS1

RS0

DCS

STF

DXJA

DXSS

(44)

PEB2256HT Datasheet(PDF) 258 Page - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 258 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL