PEB2256HT datasheet(256/490 Pages) INFINEON

256 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

256

2002-08-27

one eighth of the time slot. Data is not repeated. The time while data

is active during a 8

× 488 ns time slot is called a channel phase. RDO/

RSIG are cleared (driven to low level) while XDI/XSIG are ignored for

the remaining time of the 8

× 488 ns or for the remaining channel

phases. The channel phases are selectable with these bits.

000 = Data active in channel phase 1, valid if system data rate is

⁄8⁄4 Mbit/s

001 = Data active in channel phase 2, valid if system data rate is

⁄8⁄4 Mbit/s

010 =Data active in channel phase 3, valid if data rate is 16/8 Mbit/s

011 = Data active in channel phase 4, valid if data rate is 16/8 Mbit/s

100 = Data active in channel phase 5, valid if data rate is 16 Mbit/s

101 = Data active in channel phase 6, valid if data rate is 16 Mbit/s

110 = Data active in channel phase 7, valid if data rate is 16 Mbit/s

111 = Data active in channel phase 8, valid if data rate is 16 Mbit/s

System Interface Control 3 (Read/Write)

Value after reset: 00H

CASMF

CAS Multiframe Begin Marker

0 =

The time slot 0 multiframe begin is asserted on pin RP(A to D)/

pin function RMFB.

1 =

The time slot 16 CAS multiframe begin is asserted on pin RP(A

to D)/pin function RMFB.

SIC3

CASMF

RESX

RESR

TTRF

DAF

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PEB2256HT Datasheet(PDF) 256 Page - Infineon Technologies AG