PEB2256HT datasheet(255/490 Pages) INFINEON

255 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

255

2002-08-27

System Interface Control 2 (Read/Write)

Value after reset: 00H

FFS

Force Freeze Signaling

Setting this bit disables updating of the receive signaling buffer and

current signaling information is frozen. After resetting this bit and

receiving a complete superframe updating of the signaling buffer is

started again. The freeze signaling status can also be automatically

generated by detecting the loss-of-signal alarm or a loss of CAS

frame alignment or a receive slip (only if external register access on

pin RSIG is enabled). This automatic freeze signaling function is

logically ored with this bit.

The current internal freeze signaling status is output on pin RPA to

RPD

using

function

FREEZE

which

selected

PC(4:1).RPC(2:0) = 110. Additionally, this status is also available in

SSF

Serial Signaling Format

Only applicable if pin function RSIG/XSIG and SIC3.TTRF = 0 is

selected.

0 =

Bits 1 to 4 in all time slots except time slots 0 and16 are cleared.

1 =

Bits 1 to 4 in all time slots except time slots 0 and16 are set

high.

CRB

Center Receive Elastic Buffer

Only

applicable

the

time

slot

assigner

disabled

(PC(4:1).RPC(2:0) = 001

B), no external or internal synchronous pulse

receive is generated.

A transition from low to high forces a receive slip and the read- pointer

of the receive elastic buffer is centered. The delay through the buffer

is set to one half of the current buffer size. It should be hold high for

at least two 2.048 MHz periods before it is cleared.

SICS(2:0)

System Interface Channel Select

Only applicable if the system clock rate is greater than 2.048 MHz.

Received data is transmitted on pin RDO/RSIG or received on XDI/

XSIG with the selected system data rate. If the data rate is greater

than 2.048 Mbit/s the data is output or sampled in half, a quarter or

SIC2

FFS

SSF

CRB

SICS2

SICS1

SICS0

(3F)

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