GS1671 datasheet(121/130 Pages) SEMTECH

121 / 130 page

GS1671 HD/SD SDI Integrated Receiver

Data Sheet

53737 - 2

September 2012

121 of 130

Legend:

R = Read only

ROCW = Read Only, Clear on Write

R/W = Read or Write

W = Write only

4.21 JTAG Test Operation

When the JTAG/HOST pin of the GS1671 is set HIGH, the host interface port is

configured for JTAG test operation. In this mode, pins E7, F8, F7, and E8 become TDO,

TCK, TMS, and TDI. In addition, the RESET_TRST pin operates as the test reset pin.

Boundary scan testing using the JTAG interface is enabled in this mode.

There are two ways in which JTAG can be used:

1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test

Equipment) during PCB assembly.

2. Under control of a host processor for applications such as system power on self

tests.

When the JTAG tests are applied by ATE, care must be taken to disable any other devices

driving the digital I/O pins. If the tests are to be applied only at ATE, this can be

295h

ACSR_BYTE_21

RSVD

15-8

Reserved.

R/W

ACSR21

7-0

Audio channel status to use when

ACS_REGEN is set or when adding

audio channel status to

non-AES/EBU audio. 8 bits per

and ending at register 296h.

296hACSR_BYTE_22

RSVD

15-8

Reserved.

R/W

ACSR22

7-0

Audio channel status to use when

ACS_REGEN is set or when adding

audio channel status to

non-AES/EBU audio. 8 bits per

and ending at register 296h.

297h

RSVD

15-0

Reserved.

Table 4-30: HD Audio Core Configuration and Status Registers (Continued)

Address

Bit Name

Bit

Description

R/W

Default

Table 4-31: ANC Extraction FIFO Access Registers

Address

Bit

Description

R/W

Default

800h -

BFFh

ANC_PACKET_BANK

15-0

Extracted Ancillary Data 91024 words.

Bit 15-8: Most Significant Word (MSW).

Bit 7-0: Least Significant Word (LSW).

See Section 4.17.8.

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