| Electronic Components Datasheet Search |
|
TC1765T Datasheet(PDF) 32 Page - Infineon Technologies AG |
|
|
|||||||||||||||||||||||||||||
TC1765T Datasheet(HTML) 32 Page - Infineon Technologies AG |
|
32 / 88 page ![]() TC1765 Data Sheet 28 V1.2, 2002-12 Preliminary The General Purpose Timer Array (GPTA) provides a set of hardware modules required for high speed digital signal processing: • Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. • Phase Discrimination Logic units (PDL) decode the direction information output by a rotation tracking system. • Duty Cycle Measurement Cells (DCM) provide pulse width measurement capabilities. • A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA module clock ticks during an input signal’s period. • Global Timer units (GT) driven by various clock sources are implemented to operate as a time base for the associated “Global Timer Cells”. • Global Timer Cells (GTC) can be programmed to capture the contents of a Global Timer on an event that occurred at an external port pin or at an internal FPC output. A GTC may be also used to control an external port pin with the result of an internal compare operation. GTCs can be logically concatenated to provide a common external port pin with a complex signal waveform. • Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may be also logically tied together to drive a common external port pin with a complex signal waveform. LTCs — enabled in Timer Mode or Capture Mode — can be clocked or triggered by – A prescaled GPTA module clock, – An FPC, PDL, DCM, PLL, or GTC output signal line, – An external port pin. Some input lines driven by processor I/O pads may be shared by a LTC and a GTC cell to trigger their programmed operation simultaneously. The following list summarizes all blocks supported: Clock Generation Unit: • Filter and Prescaler Cell (FPC): – Six independent units – Three operating modes (Prescaler, Delayed Debounce Filter, Immediate Debounce Filter) – fGPTA down-scaling capability – fGPTA/2 maximum input signal frequency in Filter Mode • Phase Discriminator Logic (PDL): – Two independent units – Two operating modes (2 and 3 sensor signals) – fGPTA/4 maximum input signal frequency in 2-sensor mode, fGPTA/6 maximum input signal frequency in 3-sensor mode • Duty Cycle Measurement (DCM): – Four independent units – 0 - 100% margin and time-out handling |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |