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TC1765T Datasheet(PDF) 79 Page - Infineon Technologies AG |
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TC1765T Datasheet(HTML) 79 Page - Infineon Technologies AG |
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79 / 88 page ![]() TC1765 Data Sheet 75 V1.2, 2002-12 Preliminary Figure 29 Approximated Maximum Accumulated PLL Jitter for Typical System Clock Frequencies fSYS Note: For safe clock generation and PLL operation the definitions and restrictions as defined at pages 50, 51, and 72 must be regarded. M C D 05141_m od 0 ±1 .0 P ns D N ±1 .2 ±1 .4 ±1 .6 ±2 .0 12 34 56 ±1 .8 7 D N P K = M a x. jitte r = N u m b er of consecutive f SY S p e r iods = K -divide r of P L L f SYS = 20 M H z ( K = 8 ) f SYS = 25 M H z ( K = 8 ) f SYS = 33 M H z ( K = 6 ) f SYS = 40 M H z ( K = 4 ) |
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