TC1765T datasheet(18/88 Pages) INFINEON

18 / 88 page

TC1765

Data Sheet

V1.2, 2002-12

Preliminary

TDO

R12

JTAG Module Serial Data Output3)

TMS8)

V15

JTAG Module State Machine Control Input

OCDSE8)

R11

OCDS Enable Input

A low level on this pin during power-on reset (PORST =0)

enables the on-chip debug support (OCDS). In addition, the

level of this pin during power-on reset determines the boot

configuration.

BRKIN8)

U15

OCDS Break Input

A low level on this pin causes a break in the chip’s execution

when the OCDS is enabled. In addition, the level of this pin

during power-on reset determines the boot configuration.

BRKOUT

T12

OCDS Break Output3)

A low level on this pin indicates that a programmable OCDS

event has occurred.

NMI8)

U17

Non-Maskable Interrupt Input

A high-to-low transition on this pin causes an NMI-Trap

request to the CPU.

HDRST8)

P18

I/O

Hardware Reset Input / Reset Indication Output6)

Assertion of this open-drain bidirectional pin causes a

synchronous reset of the chip through external circuitry.

The internal reset circuitry drives this pin in response to a

power-on, hardware, watchdog and power-down wake-up

reset for a specific period of time. For a software reset, it is

programmable whether this pin is activated or not.

PORST

T17

Power-on Reset Input

A low level on PORST causes an asynchronous reset of the

entire chip. During power-up of the TC1765, this pin must be

held active (low).

BYPASS

N17

PLL Bypass Control Input

This pin is sampled during power-on reset (PORST = 0). If

BYPASS is at high level, direct drive mode operation of the

clock circuitry is selected and the PLL is bypassed.

Table 1

Pin Definitions and Functions (cont’d)

Symbol

Out

Functions

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