TC1765T datasheet(34/88 Pages) INFINEON

34 / 88 page

TC1765

Data Sheet

V1.2, 2002-12

Preliminary

Analog-to-Digital Converters

The two on-chip ADC modules of the TC1765 are analog to digital converters with 8-bit,

10-bit or 12-bit resolution including sample & hold functionality. The A/D converters

operate by the method of the successive approximation. A multiplexer selects between

up to 16 analog input channels for each ADC module. The 24 analog inputs are switched

to the analog input channels of the ADC modules by a fixed scheme. Conversion

requests are generated either under software control or by hardware (GPTA). An

automatic self-calibration adjusts the ADC modules to changing temperatures or

process variations.

Features:

• 8-bit, 10-bit, 12-bit A/D Conversion

• Successive approximation conversion method

• Fast conversion times: e.g. 10-bit conversion (without sample time): 2.05

µs

• Total Unadjusted Error (TUE) of

±2 LSB @ 10-bit resolution

• Integrated sample and hold functionality

• 24 analog input pins / 16 analog input channels of each ADC module

• Fix assignment of 24 analog input pins to the 32 ADC0/ADC1 input channels

• Dedicated control and status registers for each analog channel

• Flexible conversion request mechanisms

• Selectable reference voltages for each channel

• Programmable sample and conversion timing schemes

• Limit checking

• Flexible ADC module service request control unit

• Synchronization of the two on-chip A/D Converters

• Automatic control of an external analog input multiplexer for ADC0

• Equidistant samples initiated by timer

• Two trigger inputs, connected with the General Purpose Timer Array (GPTA)

• Two external trigger input pins of each ADC for generating conversion requests

• Power reduction and clock control feature

Figure 10 shows a global view of the ADC module kernel with the module specific

interface connections.

The ADC modules communicate with the external world via five (ADC0) or two (ADC0)

digital I/O lines and sixteen analog inputs. Clock control, address decoding, digital I/O

port control, and service request generation is managed outside the ADC module kernel.

The end of a conversion is indicated for each channel n (n = 0-15) by a pulse on the

output signals SRCHn. These signals can be used to trigger a DMA transfer to read the

conversion result automatically. Two trigger inputs and a synchronization bridge are

used for internal control purposes.

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