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TC1765T Datasheet(PDF) 86 Page - Infineon Technologies AG |
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TC1765T Datasheet(HTML) 86 Page - Infineon Technologies AG |
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86 / 88 page ![]() TC1765 Data Sheet 82 V1.2, 2002-12 Preliminary SSC Master Mode Timing VSS = 0 V; VDDP = 4.5 to 5.25 V; TA = -40 °C to +125 °C; CL = 50 pF; Figure 35 SSC Master Mode Timing Parameter Symbol Limit Values Unit min. max. SCLK / MTSR low/high from ECOUT 1) 1) This parameter is valid for high current mode output driver characteristic and normal timing edge characteristic (POCON.PECx = 0 and POCON.PDCx = 0) of the corresponding SSC output lines. t60 CC – 7ns MRST setup to SLCK rising/falling edge t61 SR 182) 2) Guaranteed by design characterization. – ns MRST hold from SLCK rising/falling edge t62 SR 102) – ns State n MCT05234 ECOUT SCLK t 60 MTSR t 60 t 61 t 62 Data Valid State n-1 State n+1 t ECOUT t 60 MRST Note: The timing diagram assumes the highest possible baudrate operation. (f SSC = fECOUT, SSCx_CLC.RMC = 1, SSCx_BR.BR_VALUE = 0000H) |
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