TC1765T datasheet(25/88 Pages) INFINEON

25 / 88 page

TC1765

Data Sheet

V1.2, 2002-12

Preliminary

High-Speed Synchronous Serial Interfaces

Figure 6 shows a global view of the functional blocks of the two High-Speed

Synchronous Serial interfaces SSC0 and SSC1.

Figure 6

General Block Diagram of the SSC Interfaces

Each of the SSC modules has three I/O lines, located at Port 0 and Port 5. Each of the

SSC modules is further supplied by separate clock control, interrupt control, address

decoding, and port control logic.

The SSC supports full-duplex and half-duplex serial synchronous communication up to

20 Mbit/s (@ 40 MHz module clock) with receive and transmit FIFO support. The serial

clock signal can be generated by the SSC itself (master mode) or can be received from

an external master (slave mode). Data width, shift direction, clock polarity, and phase are

programmable. This allows communication with SPI-compatible devices. Transmission

M C B 05051

Cloc k

C ontro l

Add res s

Dec od er

Inte rrup t

C ontro l

SS C 0

SS C0

M odule

(K e rne l)

Cloc k

C ontro l

Add res s

Dec od er

Inte rrup t

C ontro l

SSC 1

SS C1

M odule

(K e rne l)

RX D

TX D

RX D

TX D

Slav e

Ma ste r

RX D

TX D

RX D

TX D

Slav e

Ma ste r

Port 0

Co ntrol

P0.1 0 /

MR S T 0

P0.1 1 /

MT S R 0

P 0.9 /

SC L K 0

Port 5

Co ntrol

P 5.4 /

MT S R 1

P 5.3 /

MR S T 1

P 5.2 /

SC L K 1

EIR

RIR

To D M A

EIR

TIR

RIR

To D M A

TIR

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