TC1765T datasheet(17/88 Pages) INFINEON

17 / 88 page

TC1765

Data Sheet

V1.2, 2002-12

Preliminary

P5.0

P5.1

P5.2

P5.3

P5.4

D12

B13

B14

C11

A16

I/O

Port 56)

Port 5 is a 5-bit bidirectional general purpose I/O port which

also serves as input or output for ASC1 and SSC1.

RXD1

ASC1 receiver input/output

DMREQ0C

DMA request input 0C

TXD1

ASC1 transmitter output

DMREQ1C

DMA request input 1C

SCLK1

SSC1 clock input/output

MRST1

SSC1 master receive input /

SSC1 slave transmit output

MTSR1

SSC1 master transmit output /

SSC1 slave receive input

TP.0

TP.1

TP.2

TP.3

TP.4

TP.5

TP.6

TP.7

TP.8

TP.9

TP.10

TP.11

TP.12

TP.13

TP.14

TP.15

M11

M12

L11

L12

H11

H12

G11

G12

OCDS-2 Trace Port3)

TP is the OCDS Level 2 Trace Port. The Trace port is only

available in the TC1765T. The TP outputs are tristated during

reset and deep sleep mode.

Trace output 0

Trace output 1

Trace output 2

Trace output 3

Trace output 4

Trace output 5

Trace output 6

Trace output 7

Trace output 8

Trace output 9

Trace output 10

Trace output 11

Trace output 12

Trace output 13

Trace output 14

Trace output 15

TRST7)

R14

JTAG Module Reset/Enable Input

A low level at this pin resets and disables the JTAG module.

A high level enables the JTAG module.

TCK7)

T13

JTAG Module Clock Input

TDI8)

T14

JTAG Module Serial Data Input

Table 1

Pin Definitions and Functions (cont’d)

Symbol

Out

Functions

TC1765T Datasheet(PDF) 17 Page - Infineon Technologies AG

TC1765T Datasheet(HTML) 17 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL