Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
42
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
7.2.3
Digital PSoC Block Clocking Options
All digital PSoC block clocks are a user-selectable
choice of 48M, 24V1, 24V2, or 32K, as well as clocking
signals from other digital PSoC blocks or general pur-
pose I/O pins. There are a total of 16 possible clock
options for each digital PSoC block. See the Digital
PSoC Block
section for details.
8.0
Interrupts
8.1
Overview
Interrupts can be generated by the General Purpose I/O
lines, the Power monitor, the internal Sleep Timer, the
eight Digital PSoC blocks, and the four analog columns.
Every interrupt has a separate enable bit, which is con-
tained in the General Interrupt
Mask Register
(INT_MSK0) and the Digital PSoC Block Interrupt Mask
Register (INT_MSK1). When the user writes a “1” to a
particular bit position, this enables the interrupt associ-
ated with that position. There is a single Global Interrupt
Enable bit in the Flags Register (CPU_F), which can dis-
able all interrupts, or enable those interrupts that also
have their individual interrupt bit enabled. During a reset,
the enable bits in the General Interrupt Mask Register
(INT_MASK0), the enable bits in the Digital PSoC Block
Interrupt Mask Register (INT_MSK1) and the Global
Interrupt Enable bit in the Flags Register (CPU_F) are all
cleared. The Interrupt Vector Register (INT_VC) holds
the interrupt vector for the highest priority pending inter-
rupt when read, and when written will clear all pending
interrupts.
If there is only one interrupt pending and an instruction is
executed that would mask that pending interrupt (by
clearing the corresponding bit in either of the interrupt
mask registers at address E0h or E1h in Bank 0), the
CPU will take that interrupt. Since the pending interrupt
has been cleared and there are no others, the resulting
interrupt vector is 0000h and the CPU will jump to the
user code at the beginning of Flash. To address this
issue, use the macro defined in m8c.inc called
"M8C_DisableIntMask" in PSoC Designer. This macro
brackets the register write with a disable then an enable
of global interrupts.
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