Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
58
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
9.3.5
Digital Communications Type A Block xx Control Register 0 When Used as UART
Receiver
Digital Communications Type A 04 Control Register 0
(DCA04CR0, Address = Bank 0, 33h)
Digital Communications Type A 05 Control Register 0
(DCA05CR0, Address = Bank 0, 37h)
Digital Communications Type A Block 06 Control Register 0
(DCA06CR0, Address = Bank 0, 3Bh)
Digital Communications Type A Block 07 Control Register 0
(DCA07CR0, Address = Bank 0, 3Fh)
Table 57:
Digital Communications Type A Block xx Control Register 0...
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
RW
RW
RW
Bit Name
Parity
Error
Overrun
Framing
Error
RX Active
RX Reg
Full
Parity
Type
Parity
Enable
Enable
Bit 7
: Parity Error
0 = Indicates no parity error detected in the last byte received
1 = Indicates a parity error detected in the last byte received
Reset when this register is read
Bit 6
: Overrun
0 = Indicates that no overrun has taken place
1 = Indicates the RX Data register was overwritten with a new byte before the previous one had been read
Reset when this register is read
Bit 5
: Framing Error
0 = Indicates correct stop bit
1 = Indicates a missing STOP bit
Reset when this register is read
Bit 4
: RX Active
0 = Indicates no communication currently in progress
1 = Indicates a start bit has been received and a byte is currently being received
Bit 3
: RX Reg Full
0 = Indicates the RX Data register is empty
1 = Indicates a byte has been loaded into the RX Data register
Interrupt source for RXUART. Reset when the RX Data register is read (Data Register 2)
Bit 2
: Parity Type
0 = Even
1 = Odd
Bit 1
: Parity Enable
0 = Parity Disabled
1 = Parity Enabled
Bit 0
: Enable
0 = Function Disabled
1 = Function Enabled
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