I/O Registers
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
31
6.0
I/O Registers
6.1
Port Data Registers
Port 0 Data Register (PRT0DR, Address = Bank 0, 00h)
Port 1 Data Register (PRT1DR, Address = Bank 0, 04h)
Port 2 Data Register (PRT2DR, Address = Bank 0, 08h)
Port 3 Data Register (PRT3DR, Address = Bank 0, 0Ch)
Port 4 Data Register (PRT4DR, Address = Bank 0, 10h)
Port 5 Data Register (PRT5DR, Address = Bank 0, 14h) Note: Port 5 is 4-bits wide, Bit [3:0]
6.2
Port Interrupt Enable Registers
Port 0 Interrupt Enable Register (PRT0IE, Address = Bank 0, 01h)
Port 1 Interrupt Enable Register (PRT1IE, Address = Bank 0, 05h)
Port 2 Interrupt Enable Register (PRT2IE, Address = Bank 0, 09h)
Port 3 Interrupt Enable Register (PRT3IE, Address = Bank 0, 0Dh)
Port 4 Interrupt Enable Register (PRT4IE, Address = Bank 0, 11h)
Port 5 Interrupt Enable Register (PRT5IE, Address = Bank 0, 15h) Note: Port 5 is 4-bits wide
Table 28:
Port Data Registers
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]
: Data [7:0] When written is the bits for output on port pins. When read is the state of the port pins
Table 29:
Port Interrupt Enable Registers
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Bit Name
Int En [7]
Int En [6]
Int En [5] Int En [4]
Int En [3]
Int En [2]
Int En [1]
Int En [0]
Bit [7:0]
: Int En [7:0] When written sets the pin interrupt state
0 = Interrupt disabled for pin
1 = Interrupt enabled for pin
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