September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
5
1.0 Functional Overview ......................................................................................................................14
1.1 Key Features ..............................................................................................................................14
1.2 Pin-out Descriptions ...................................................................................................................15
2.0 CPU Architecture ............................................................................................................................19
2.1 Introduction ................................................................................................................................19
2.2 CPU Registers ...........................................................................................................................20
2.3 Addressing Modes .....................................................................................................................21
2.4 Instruction Set Summary ...........................................................................................................25
3.0 Memory Organization .....................................................................................................................26
3.1 Flash Program Memory Organization ........................................................................................26
3.2 RAM Data Memory Organization ...............................................................................................26
4.0 Register Organization ....................................................................................................................26
4.1 Introduction ................................................................................................................................26
4.2 Register Bank 0 Map .................................................................................................................27
4.3 Register Bank 1 Map ................................................................................................................28
5.0 I/O Ports ...........................................................................................................................................29
5.1 Introduction ................................................................................................................................29
6.0 I/O Registers ...................................................................................................................................31
6.1 Port Data Registers ...................................................................................................................31
6.2 Port Interrupt Enable Registers .................................................................................................31
6.3 Port Global Select Registers .....................................................................................................32
7.0 Clocking ..........................................................................................................................................35
7.1 Oscillator Options .......................................................................................................................35
7.2 System Clocking Signals ............................................................................................................38
8.0 Interrupts .........................................................................................................................................42
8.1 Overview ....................................................................................................................................42
8.2 Interrupt Control Architecture .....................................................................................................44
8.3 Interrupt Vectors .........................................................................................................................44
8.4 Interrupt Masks ..........................................................................................................................45
8.5 Interrupt Vector Register ...........................................................................................................46
8.6 GPIO Interrupt ............................................................................................................................47
9.0 Digital PSoC Blocks .......................................................................................................................48
9.1 Introduction ................................................................................................................................48
9.2 Digital PSoC Block Bank 1 Registers .........................................................................................49
9.3 Digital PSoC Block Bank 0 Registers .........................................................................................54
9.4 Global Inputs and Outputs .........................................................................................................60
9.5 Available Programmed Digital Functionality ...............................................................................60
10.0 Analog PSoC Blocks ....................................................................................................................71
10.1 Introduction ..............................................................................................................................71
10.2 Analog System Clocking Signals .............................................................................................72
10.3 Array of Analog PSoC Blocks .................................................................................................72
10.4 Analog Reference and Bias Control .........................................................................................73
10.5 AGND, REFHI, REFLO ............................................................................................................73
10.6 Analog PSoC Block Clocking Options ......................................................................................74
10.7 Analog Clock Select Register ..................................................................................................75
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