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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
18
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
P5[0]
I/O
29 Port 5[0]
P5[2]
I/O
30 Port 5[2]
P4[0]
I/O
31 Port 4[0]
P4[2]
I/O
32 Port 4[2]
P4[4]
I/O
33 Port 4[4]
P4[6]
I/O
34 Port 4[6]
XRES
I
35 External Reset
P3[0]
I/O
36 Port 3[0]
P3[2]
I/O
37 Port 3[2]
P3[4]
I/O
38 Port 3[4]
P3[6]
I/O
39 Port 3[6]
P2[0]
I/O
40
Port 2[0] (Non-Multiplexed
Analog Input)
P2[2]
I/O
41
Port 2[2] (Non-Multiplexed
Analog Input)
P2[4]
I/O
42 Port 2[4] / External AGNDIn
P2[6]
I/O
43 Port 2[6] / External VREFIn
P0[0]
I/O
44 Port 0[0] (Analog Input)
P0[2]
I/O
45
Port 0[2] (Analog Input/Out-
put)
P0[4]
I/O
46
Port 0[4] (Analog Input/Out-
put)
P0[6]
I/O
47 Port 0[6] (Analog Input)
Vcc
Power
48 Supply Voltage
Figure 6: 26643 PDIP/SSOP
Table 6:
Pin-out 48 Pin, continued
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[7]
P3[5]
P3[3]
P3[1]
SMP
P4[7]
P4[5]
P4[3]
P4[1]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
XtalIn/SCLK/P1[1]
Vcc
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]/External V
ref
P2[4] /External AGNDIN
P2[2]
P2[0]
P3[6]
P3[4]
P3[2]
P3[0]
P4[6]
P4[4]
P4[2]
P4[0]
P5[2]
P5[0]
P1[6]
P1[4]
P1[2]
P1[0]/XtalOut/SDATA
Vss
Xres
IN
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