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Analog PSoC Blocks
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
93
10.10.2
Registers
10.10.2.1
Analog Switch Cap Type B Block xx Control 0 Register
FCap controls the size of the switched feedback capaci-
tor in the integrator.
ClockPhase controls the internal clock phasing relative
to the input clock phasing. ClockPhase affects the output
of the analog column bus which is controlled by the
AnalogBus bit in Control 2 Register (ASB11CR2,
ASB13CR2, ASB20CR2, ASB22CR2).
ASign controls the switch phasing of the switches on the
bottom plate of the A capacitor. The bottom plate sam-
ples the input or the reference.
The ACap bits set the value of the capacitor in the A
path.
Figure 25: Analog Switch Cap Type B PSoC Blocks
φ
1* FSW0
Power
φ
1*BSW
φ
2 +!BSW
BMuxSCB
B Inputs
BQTAP
CCap
0..31 C
BCap
0..31 C
ACap
0..31 C
FCap
16,32 C
φ
1*AutoZero
(φ
2+!AutoZero)
* FSW1
φ
2+AutoZero
φ
1*BSW
φ
2+!BSW
ABUS
CBUS
AnalogBus*
φ
2B
CompBus
OUT
φ
1 *
!AutoZero
φ
2
φ
1
A Inputs
ASign
ARefMux
REFHI
REFLO
AGND
A Mux
Table 72:
Analog Switch Cap Type B Block xx Control 0 Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
FCap
ClockPhase
ASign
ACap[4]
ACap[3]
ACap[2]
ACap[1]
ACap[0]
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