I/O Registers
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
33
6.3.2
Port Drive Mode 1 Registers
Port 0 Drive Mode 1 Register (PRT0DM1, Address = Bank 1, 01h)
Port 1 Drive Mode 1 Register (PRT1DM1, Address = Bank 1, 05h)
Port 2 Drive Mode 1 Register (PRT2DM1, Address = Bank 1, 09h)
Port 3 Drive Mode 1 Register (PRT3DM1, Address = Bank 1, 0Dh)
Port 4 Drive Mode 1 Register (PRT4DM1, Address = Bank 1, 11h)
Port 5 Drive Mode 1 Register (PRT5DM1, Address = Bank 1, 15h) Note: Port 5 is 4-bits wide
6.3.3
Port Interrupt Control 0 Registers
Port 0 Interrupt Control 0 Register (PRT0IC0, Address = Bank 1, 02h)
Port 1 Interrupt Control 0 Register (PRT1IC0, Address = Bank 1, 06h)
Port 2 Interrupt Control 0 Register (PRT2IC0, Address = Bank 1, 0Ah)
Port 3 Interrupt Control 0 Register (PRT3IC0, Address = Bank 1, 0Eh)
Port 4 Interrupt Control 0 Register (PRT4IC0, Address = Bank 1, 12h)
Port 5 Interrupt Control 0 Register (PRT5IC0, Address = Bank 1, 16h) Note: Port 5 is 4-bits wide
Table 32:
Port Drive Mode 1 Registers
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Bit Name
DM1 [7]
DM1 [6]
DM1 [5]
DM1 [4]
DM1 [3]
DM1 [2]
DM1 [1]
DM1 [0]
Bit [7:0]
: DM1 [7:0] See truth table for Port Drive Mode 0 Registers, above
Table 33:
Port Interrupt Control 0 Registers
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Bit Name
IC0 [7]
IC0 [6]
IC0 [5]
IC0 [4]
IC0 [3]
IC0 [2]
IC0 [1]
IC0 [0]
Bit [7:0]
: IC0 [7:0] The two Interrupt Control bits that control a particular port pin are treated as a pair and are
decoded as follows:
IC1 [x], IC0 [x] = 0 0 = Disabled (Default)
IC1 [x], IC0 [x] = 0 1 = Falling Edge (-)
IC1 [x], IC0 [x] = 1 0 = Rising Edge (+)
IC1 [x], IC0 [x] = 1 1 = Change from Last Direct Read
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
