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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
34
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
6.3.4
Port Interrupt Control 1 Registers
Port 0 Interrupt Control 1 Register (PRT0IC1, Address = Bank 1, 03h)
Port 1 Interrupt Control 1 Register (PRT1IC1, Address = Bank 1, 07h)
Port 2 Interrupt Control 1 Register (PRT2IC1, Address = Bank 1, 0Bh)
Port 3 Interrupt Control 1 Register (PRT3IC1, Address = Bank 1, 0Fh)
Port 4 Interrupt Control 1 Register (PRT4IC1, Address = Bank 1, 13h)
Port 5 Interrupt Control 1 Register (PRT5IC1, Address = Bank 1, 17h) Note: Port 5 is 4-bits wide
Table 34:
Port Interrupt Control 1 Registers
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/
Write
W
W
W
W
W
W
W
W
Bit Name
IC1 [7]
IC1 [6]
IC1 [5]
IC1 [4]
IC1 [3]
IC1 [2]
IC1 [1]
IC1 [0]
Bit [7:0]
: IC1 [7:0] See truth table for Port Interrupt Control 0 Registers, above
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