Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
98
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
10.10.2.4
Analog Switch Cap Type B Block xx Control 3 Register
ARefMux selects the reference input of the A capacitor
branch.
FSW1 is used to control a switch in the integrator capac-
itor path. It connects the output of the op-amp to the inte-
grating cap. The state of the switch is affected by the
state of the AutoZero bit in Control 2 Register
(ASB11CR2, ASB13CR2, ASB20CR2, ASB22CR2). If
the FSW1 bit is set to 0, the switch is always disabled. If
the FSW1 bit is set to 1, the AutoZero bit determines the
state of the switch. If the AutoZero bit is 0, the switch is
enabled at all times. If the AutoZero bit is 1, the switch is
enabled only when the internal PHI2 is high.
FSW0 is used to control a switch in the integrator capac-
itor path. It connects the output of the op-amp to analog
ground.
BSW is used to control switching in the B branch. If dis-
abled, the B capacitor branch is a continuous time
branch like the C branch of the SC A Block. If enabled,
then on internal PHI1, both ends of the cap are switched
to analog ground. On internal PHI2, one end is switched
to the B input and the other end is switched to the sum-
ming node.
BMuxSCB controls muxing to the input of the B capacitor
branch. The B branch can be switched or unswitched.
Analog Switch Cap Type B Block 11 Control 3 Register (ASB11CR3, Address = Bank 0/1, 87h)
Analog Switch Cap Type B Block 13 Control 3 Register (ASB13CR3, Address = Bank 0/1, 8Fh)
Analog Switch Cap Type B Block 20 Control 3 Register (ASB20CR3, Address = Bank 0/1, 93h)
Analog Switch Cap Type B Block 22 Control 3 Register (ASB22CR3, Address = Bank 0/1, 9Bh)
Table 75:
Analog Switch Cap Type B Block xx Control 3 Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
ARefMux[1] ARefMux[0]
FSW[1]
FSW[0]
BSW
BMuxSCB
Power[1]
Power[0]
Bit [7:6]
: ARefMux [1:0] Encoding for selecting reference input
0 0 = Analog ground is selected
0 1 = REFHI input selected (This is usually the high reference)
1 0 = REFLO input selected (This is usually the low reference)
1 1 = Reference selection is driven by the comparator (When output comparator node is set high, the input is set to
REFHI. When set low, the input is set to REFLO)
Bit 5
: FSW1 Bit for controlling gated switches
0 = Switch is disabled
FSW1 bit is set to 1; the state of the switch is determined by the AutoZero bit. If the AutoZero bit is 0, the switch is
enabled at all times. If the AutoZero bit is 1, the switch is enabled only when the internal PHI2 is high
Bit 4
: FSW0 Bits for controlling gated switches
0 = Switch is disabled
1 = Switch is enabled when PHI1 is high
Bit 3
: BSW Enable switching in branch
0 = B branch is a continuous time path
1 = B branch is switched with internal PHI2 sampling
Bit 2
: BMuxSCB Encoding for selecting B inputs. (Note that the available mux inputs vary by individual PSoC block)
ASB11 ASB13 ASB20 ASB22
0 = ACA00 ACA02 ASA11 ASA13
1 = ACA01 ACA03 ASB10 ASB12
Bit [1:0]
: Power [1:0] Encoding for selecting 1 of 4 power levels
0 0 = Off
0 1 = 10
µA, typical
1 0 = 50
µA, typical
1 1 = 200
µA, typical
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