Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
94
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
Analog Switch Cap Type B Block 11 Control 0 Register (ASB11CR0, Address = Bank 0/1, 84h)
Analog Switch Cap Type B Block 13 Control 0 Register (ASB13CR0, Address = Bank 0/1, 8Ch)
Analog Switch Cap Type B Block 20 Control 0 Register (ASB20CR0, Address = Bank 0/1, 90h)
Analog Switch Cap Type B Block 22 Control 0 Register (ASB22CR0, Address = Bank 0/1, 98h)
Bit 7
: FCap F Capacitor value selection bit
0 = 16 capacitor units
1 = 32 capacitor units
Bit 6
: ClockPhase Clock phase select, will invert clocks internal to the blocks. During normal operation of an SC
block for the amplifier of a column enabled to drive the output bus, the connection is only made for the last half of
PHI2 (during PHI1 and for the first half of PHI2, the output bus floats at the last voltage to which it was driven). This
forms a sample and hold operation using the output bus and its associated capacitance. This design prevents the
output bus from being perturbed by the intermediate states of the SC operation (often a reset state for PHI1 and
settling to the valid state during PHI2)
Following are the exceptions: 1) If the ClockPhase bit in CR0 (for the SC block in question) is set to 1, then the out-
put is enabled for the whole of PHI2. 2) If the SHDIS signal is set in bit 6 of the Analog Clock Select Register, then
sample and hold operation is disabled for all columns and all enabled outputs of SC blocks are connected to their
respective output busses for the entire period of their respective PHI2s
0 = Internal PHI1 = External PHI1
1 = Internal PHI1 = External PHI2
This bit also affects the latching of the comparator output (CBUS). Both clock phases, PHI1 and PHI2, are involved
in the output latching mechanism. The capture of the next value to be output from the latch (capture point event)
happens during the falling edge of one clock phase, and the rising edge of the other clock phase will cause the
value to come out (output point event). This bit determines which clock phase triggers the capture point event, and
the other clock will trigger the output point event. The value output to the comparator bus will remain stable
between output point events.
0 = Capture Point Event triggered by Falling PHI2, Output Point Event triggered by Rising PHI1
1 = Capture Point Event triggered by Falling PHI1, Output Point Event triggered by Rising PHI2
Bit 5
: ASign
0 = Input sampled on Internal PHI1, Reference Input sampled on internal PHI2
1 = Input sampled on Internal PHI2, Reference Input sampled on internal PHI1
Bit [4:0]
: ACap [4:0] Binary encoding for 32 possible capacitor sizes for A Capacitor:
0 0 0 0 0 = 0 Capacitor units in array
0 0 0 0 1 = 1 Capacitor units in array
0 0 0 1 0 = 2 Capacitor units in array
0 0 0 1 1 = 3 Capacitor units in array
0 0 1 0 0 = 4 Capacitor units in array
0 0 1 0 1 = 5 Capacitor units in array
0 0 1 1 0 = 6 Capacitor units in array
0 0 1 1 1 = 7 Capacitor units in array
0 1 0 0 0 = 8 Capacitor units in array
0 1 0 0 1 = 9 Capacitor units in array
0 1 0 1 0 = 10 Capacitor units in array
0 1 0 1 1 = 11 Capacitor units in array
0 1 1 0 0 = 12 Capacitor units in array
0 1 1 0 1 = 13 Capacitor units in array
0 1 1 1 0 = 14 Capacitor units in array
0 1 1 1 1 = 15 Capacitor units in array
1 0 0 0 0 = 16 Capacitor units in array
1 0 0 0 1 = 17 Capacitor units in array
1 0 0 1 0 = 18 Capacitor units in array
1 0 0 1 1 = 19 Capacitor units in array
1 0 1 0 0 = 20 Capacitor units in array
1 0 1 0 1 = 21 Capacitor units in array
1 0 1 1 0 = 22 Capacitor units in array
1 0 1 1 1 = 23 Capacitor units in array
1 1 0 0 0 = 24 Capacitor units in array
1 1 0 0 1 = 25 Capacitor units in array
1 1 0 1 0 = 26 Capacitor units in array
1 1 0 1 1 = 27 Capacitor units in array
1 1 1 0 0 = 28 Capacitor units in array
1 1 1 0 1 = 29 Capacitor units in array
1 1 1 1 0 = 30 Capacitor units in array
1 1 1 1 1 = 31 Capacitor units in array
Table 72:
Analog Switch Cap Type B Block xx Control 0 Register, continued
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