Digital PSoC Blocks
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
57
9.3.4
Digital Communications Type A Block xx Control Register 0 When Used as UART Trans-
mitter
Digital Communications Type A 04 Control Register 0
(DCA04CR0, Address = Bank 0, 33h)
Digital Communications Type A 05 Control Register 0
(DCA05CR0, Address = Bank 0, 37h)
Digital Communications Type A Block 06 Control Register 0
(DCA06CR0, Address = Bank 0, 3Bh)
Digital Communications Type A Block 07 Control Register 0
(DCA07CR0, Address = Bank 0, 3Fh)
Table 56:
Digital Communications Type A Block xx Control Register 0...
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/
Write
--
--
R
R
--
RW
RW
RW
Bit Name
Reserved
Reserved
TX Complete
TX Reg
Empty
Reserved
Parity Type
Parity
Enable
Enable
Bit 7
: Reserved
Bit 6
: Reserved
Bit 5
: TX Complete
0 = Indicates that if a transmission has been initiated, it is still in progress
1 = Indicates that the current transmission is complete (including framing bits)
Optional interrupt source for TX UART. Reset when this register is read.
Bit 4
: TX Reg Empty
0 = Indicates TX Data register is not available to accept another byte (writing to register will cause data to be lost)
1 = Indicates TX Data register is available to accept another byte
Note that the interrupt does not occur until at least 1 byte has been previously written to the TX Data Register
Default interrupt source for TX UART. Reset when the TX Data Register (Data Register 1) is written.
Bit 3
: Reserved
Bit 2
: Parity Type
0 = Even
1 = Odd
Bit 1
: Parity Enable
0 = Parity Disabled
1 = Parity Enabled
Bit 0
: Enable
0 = Function Disabled
1 = Function Enabled
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