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Interrupts
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
45
8.4
Interrupt Masks
General Interrupt Mask Register (INT_MSK0, Address = Bank 0, E0h)
Table 44:
General Interrupt Mask Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
Reserved
Sleep
GPIO
Acolumn3 Acolumn2 Acolumn1 Acolumn0
Voltage Monitor
Bit 7
: Reserved
Bit 6
: Sleep Interrupt Enable Bit (see 11.4)
0 = Disabled
1 = Enabled
Bit 5
: GPIO Interrupt Enable Bit (see 8.6)
0 = Disabled
1 = Enabled
Bit [4]
: Acolumn 3 Interrupt Enable Bit (see 10.0)
0 = Disabled
1 = Enabled
Bit [3]
: Acolumn 2 Interrupt Enable Bit (see 10.0)
0 = Disabled
1 = Enabled
Bit [2]
: Acolumn 1 Interrupt Enable Bit (see 10.0)
0 = Disabled
1 = Enabled
Bit [1]
: Acolumn 0 Interrupt Enable Bit (see 10.0)
0 = Disabled
1 = Enabled
Bit 0
: Voltage Monitor Interrupt Enable Bit (see 11.5)
0 = Disabled
1 = Enabled
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