Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
44
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
8.2
Interrupt Control Architecture
The interrupt controller contains a separate flip-flop for
each interrupt. When an interrupt is generated, it is regis-
tered as a pending interrupt. It will stay pending until it is
serviced, a reset occurs, or there is a write to the
INT_VC Register. A pending interrupt will only generate
an interrupt request when enabled by the appropriate
mask bit in the Digital PSoC Block Interrupt Mask Regis-
ter (INT_MSK1) or General Interrupt Mask Register
(INT_MSK0), and the Global IE bit in the CPU_F register
is set.
Additionally, for GPIO Interrupts, the appropriate enable
and interrupt-type bits for each I/O pin must be set (see
section 6.0, Table 29 on page 31, Table 33 on page 33,
and Table 34 on page 34). For Analog Column Inter-
rupts, the interrupt source must be set (see section 10.11
and Table 76 on page 99).
During the servicing of any interrupt, the MSB and LSB
of Program Counter and Flag registers (CPU_PC and
CPU_F) are stored onto the program stack by an auto-
matic CALL instruction (13 cycles) generated during the
interrupt acknowledge process. The user firmware may
preserve and restore processor state during an interrupt
using the PUSH and POP instructions. The memory ori-
ented CPU architecture requires minimal state saving
during interrupts, providing very fast interrupt context
switching. The Program Counter and Flag registers
(CPU_PC and CPU_F) are restored when the RETI
instruction is executed. If two or more interrupts are
pending at the same time, the higher priority interrupt
(lower priority number) will be serviced first.
After a copy of the Flag Register is stored on the stack,
the Flag Register is automatically cleared. This disables
all interrupts, since the Global IE flag bit is now cleared.
Executing a RETI instruction restores the Flag register,
and re-enables the Global Interrupt bit.
Nested interrupts can be accomplished by re-enabling
interrupts inside an interrupt service routine. To do this,
set the IE bit in the Flag Register. The user must store
sufficient information to maintain machine state if this is
done.
Each digital PSoC block has its own unique Interrupt
Vector and Interrupt Enable bit. There are also individual
interrupt vectors for each of the Analog columns, Supply
Voltage Monitor, Sleep Timer and General Purpose I/Os.
8.3
Interrupt Vectors
The interrupt process vectors the Program Counter to
the appropriate address in the
Interrupt Vector Table.
Typically, these addresses contain JMP instructions to
the start of the interrupt handling routine for the interrupt.
Table 43:
Interrupt Vector Table
Address
Description
0x0004
1
Supply Monitor Interrupt Vector
0x0008
2
DBA00 PSoC Block Interrupt Vector
0x000C
3
DBA01 PSoC Block Interrupt Vector
0x0010
4
DBA02 PSoC Block Interrupt Vector
0x0014
5
DBA03 PSoC Block Interrupt Vector
0x0018
6
DCA04 PSoC Block Interrupt Vector
0x001C
7
DCA05 PSoC Block Interrupt Vector
0x0020
8
DCA06 PSoC Block Interrupt Vector
0x0024
9
DCA07 PSoC Block Interrupt Vector
0x0028
10
Acolumn 0 Interrupt Vector
0x002C
11
Acolumn 1 Interrupt Vector
0x0030
12
Acolumn 2 Interrupt Vector
0x0034
13
Acolumn 3 Interrupt Vector
0x0038
14
GPIO Interrupt Vector
0x003C
15
Sleep Timer Interrupt Vector
0x0040
On-Chip Program Memory Starts
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