Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
74
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
10.6 Analog PSoC Block Clocking Options
All analog PSoC blocks in a particular Analog Column
share the same clock signal. Choosing the clocking for
an analog PSoC block is a two-step process.
1.
First, if the user wants to use the ACLK0 and
ACLK1
system-clocking signals, the digital PSoC
blocks that serve as the source for these signals
must be selected. This selection is made in the Ana-
log Clock Select Register (CLK_CR1).
2.
Next, the user must select the source for the
Acolumn0
, Acolumn1, Acolumn2, and Acolumn3
system-clocking signals. The user will choose the
clock for Acolumnx[1:0] bits in the Analog Column
Clock Select Register (CLK_CR0). Each analog
PSoC block in a particular Analog Column is
clocked from the Acolumn[x] system-clocking sig-
nal for that column. (Note that the Acolumn[x] sig-
nals have a 1:4 divider on them.)
10.6.1 Analog Column Clock Select Register
Analog Column Clock Select Register (CLK_CR0, Address = Bank 1, 60h)
Table 63:
Analog Column Clock Select Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
Acolumn3
[1]
Acolumn3
[0]
Acolumn2
[1]
Acolumn2
[0]
Acolumn1
[1]
Acolumn1
[0]
Acolumn0
[1]
Acolumn0
[0]
Bit [7:6]
: Acolumn3 [1:0]
0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
Bit [5:4]
: Acolumn2 [1:0]
0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
Bit [3:2]
: Acolumn1 [1:0]
0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
Bit [1:0]
: Acolumn0 [1:0]
0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
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