46 / 148 page
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
46
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
Digital PSoC Block Interrupt Mask Register (INT_MSK1, Address = Bank 0, E1h)
8.5
Interrupt Vector Register
Interrupt Vector Register (INT_VC, Address = Bank 0, E2h)
Table 45:
Digital PSoC Block Interrupt Mask Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
DCA07
DCA06
DCA05
DCA04
DBA03
DBA02
DBA01
DBA00
Bit 7
: DCA07 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 6
: DCA06 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 5
: DCA05 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 4
: DCA04 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 3
: DBA03 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 2
: DBA02 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 1
: DBA01 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Bit 0
: DBA00 Interrupt Enable Bit
0 = Disabled
1 = Enabled
Table 46:
Interrupt Vector Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
Data[7]
Data[6]
Data[5]
Data[4]
Data[3]
Data[2]
Data[1]
Data[0]
Bit [7:0]
: Data [7:0]
8-bit data value holds the interrupt vector for the highest priority pending interrupt. Writing to this register will clear all
pending interrupts
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
