Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
40
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
Oscillator Control 0 Register (OSC_CR0, Address = Bank 1, E0h)
Oscillator Control 1 Register (OSC_CR1, Address = Bank 1, E1h)
Table 40:
Oscillator Control 0 Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
32k Select
PLL Mode
Reserved
Sleep [1]
Sleep [0]
CPU [2]
CPU [1]
CPU [0]
Bit 7
: 32k Select
0 = Internal low precision 32 kHz oscillator
1 = External Crystal Oscillator
Bit 6
: PLL Mode
0 = Disabled
1 = Enabled, Internal Main Oscillator is locked to External Crystal Oscillator
Bit 5
: Reserved
Bit [4:3]
: Sleep [1:0]
0 0 = 512 Hz or 1.95 ms period
0 1 = 64 Hz or 15.6 ms period
1 0 = 8 Hz or 125 ms period
1 1 = 1 Hz or 1 s period
Bit [2:0]
: CPU [2:0]
0 0 0 = 3 MHz
0 0 1 = 6 MHz
0 1 0 = 12 MHz
0 1 1 = 24 MHz
1 0 0 = 1.5 MHz
1 0 1 = 750 kHz
1 1 0 = 187.5 kHz
1 1 1 = 93.7 kHz
Table 41:
Oscillator Control 1 Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
24V1 [3]
24V1 [2]
24V1 [1]
24V1 [0]
24V2 [3]
24V2 [2]
24V2 [1]
24V2 [0]
Bit [7:4]
: 24V1 [3:0] 4-bit data value determines the divider value for the 24V1 system-clocking signal. Note that the
4-bit data value equals n-1, where n is the desired divider value, as illustrated in PSoC MCU Clock Tree of Signals.
See Table 42 on page 41.
Bit [3:0]
: 24V2 [3:0] 4-bit data value determines the divider value for the 24V2 system-clocking signal. Note that the
4-bit data value equals n-1, where n is the desired divider value, as illustrated in the PSoC MCU Clock Tree of Sig-
nals. See Table 42 on page 41.
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