WM8994 datasheet(164/359 Pages) WOLFSON

164 / 359 page

WM8994

Production Data

PD, April 2012, Rev 4.4

164

WM8994

Processor

WM8994 or

Similar

CODEC

ADCDAT

ADCLRC

DACDAT

BCLK

ADCDAT

ADCLRC

DACDAT

BCLK

Figure 49 TDM with Processor as Master

Note: The WM8994 is a 24-bit device. If the user operates the WM8994 in 32-bit mode then the 8

LSBs will be ignored on the receiving side and not driven on the transmitting side. It is therefore

recommended to add a pull-down resistor if necessary to the DACDAT line and the ADCDAT line in

TDM mode.

AUDIO DATA FORMATS (NORMAL MODE)

The audio data modes supported by the WM8994 are described below. Note that the polarity of the

BCLK and LRCLK signals can be inverted if required; the following descriptions all assume the

default, non-inverted polarity of these signals.

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.

Figure 50 Right Justified Audio Interface (assuming n-bit word length)

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

WM8994 Datasheet(PDF) 164 Page - Wolfson Microelectronics plc