TMS320C6711 datasheet(40/129 Pages) TI

40 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

CPU CSR register description (continued)

Table 19. CPU CSR Register Bit Field Description

BIT #

NAME

DESCRIPTION

31:24

CPU ID

CPU ID + REV ID. Read only.

Identifies which CPU is used and defines the silicon revision of the CPU.

23:16

REVISION ID

CPU ID + REVISION ID (31:16) are combined for a value of: 0x0202 for C6711/11B and 0x0203 for

C6711C/11D

15:10

PWRD

Control power-down modes. The values are always read as zero.

000000 = no power-down (default)

001001 = PD1, wake-up by an enabled interrupt

010001 = PD1, wake-up by an enabled or not enabled interrupt

011010

= PD2, wake-up by a device reset

011100

= PD3, wake-up by a device reset

Others

= Reserved

SAT

Saturate bit.

Set when any unit performs a saturate. This bit can be cleared only by the MVC instruction and can

be set only by a functional unit. The set by the a functional unit has priority over a clear (by the MVC

instruction) if they occur on the same cycle. The saturate bit is set one full cycle (one delay slot) after

a saturate occurs. This bit will not be modified by a conditional instruction whose condition is false.

Endian bit. This bit is read-only.

Depicts the device endian mode.

0 = Big Endian mode.

1 = Little Endian mode [default].

7:5

PCC

Program Cache control mode.

L1D, Level 1 Program Cache

000/010 =

Cache Enabled / Cache accessed and updated on reads.

All other PCC values reserved.

4:2

DCC

Data Cache control mode.

L1D, Level 1 Data Cache

000/010 =

Cache Enabled / 2-Way Cache

All other DCC values reserved

PGIE

Previous GIE (global interrupt enable); saves the Global Interrupt Enable (GIE) when an interrupt is

taken. Allows for proper nesting of interrupts.

0 = Previous GIE value is 0. (default)

1 = Previous GIE value is 1.

GIE

Global interrupt enable bit.

Enables (1) or disables (0) all interrupts except the reset interrupt and NMI (nonmaskable interrupt).

0 = Disables all interrupts (except the reset interrupt and NMI) [default]

1 = Enables all interrupts (except the reset interrupt and NMI)

TMS320C6711 Datasheet(PDF) 40 Page - Texas Instruments

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