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TMS320C6711 Datasheet(PDF) 26 Page - Texas Instruments |
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TMS320C6711 Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 129 page  TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D FLOATING-POINT DIGITAL SIGNAL PROCESSORS SPRS088L − FEBRUARY 1999 − REVISED MAY 2004 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL PIN NO. TYPE† IPD/ DESCRIPTION SIGNAL NAME GFN GDP TYPE† IPD/ IPU‡ DESCRIPTION EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY# CE3 V6 V6 O/Z IPU CE2 W6 W6 O/Z IPU Memory space enables • Enabled by bits 28 through 31 of the word address CE1 W18 W18 O/Z IPU • Enabled by bits 28 through 31 of the word address • Only one asserted during any external data access CE0 V17 V17 O/Z IPU • Only one asserted during any external data access BE3 V5 V5 O/Z IPU Byte-enable control BE2 Y4 Y4 O/Z IPU Byte-enable control • Decoded from the two lowest bits of the internal address BE1 U19 U19 O/Z IPU • Decoded from the two lowest bits of the internal address • Byte-write enables for most types of memory C b di tl t d t SDRAM d d it k i l (SDQM) BE0 V20 V20 O/Z IPU yyp y • Can be directly connected to SDRAM read and write mask signal (SDQM) EMIF − BUS ARBITRATION# HOLDA J18 J18 O IPU Hold-request-acknowledge to the host HOLD J17 J17 I IPU Hold request from the host BUSREQ J19 J19 O IPU Bus request output EMIF − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL# ECLKIN Y11 Y11 I IPD External EMIF input clock source ECLKOUT Y10 Y10 O/Z IPD EMIF output clock (based on ECLKIN) [C6711/11B] EMIF output clock depends on the EKSRC bit (DEVCFG.[4]) and on EKEN bit (GBLCTL.[5]). [C6711C/C6711D only] EKSRC = 0 – ECLKOUT is based on the internal SYSCLK3 signal from the clock generator (default). EKSRC = 1 – ECLKOUT is based on the the external EMIF input clock source pin (ECLKIN) EKEN = 0 – ECLKOUT held low EKEN = 1 – ECLKOUT enabled to clock (default) ARE/SDCAS/ SSADS V11 V11 O/Z IPU Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM ad- dress strobe AOE/SDRAS/ SSOE W10 W10 O/Z IPU Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable AWE/SDWE/ SSWE V12 V12 O/Z IPU Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable ARDY Y5 Y5 I IPU Asynchronous memory ready input † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ For C6711/11B, IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) For C6711C/11D, IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-kΩ resistor (approximate) for the IPD or 18-kΩ resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be used to pull a signal to the opposite supply rail.] # To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. |
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