TMS320C6711 datasheet(64/129 Pages) TI

64 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

The C6711/C6711B/C6711C/C6711D has three types of boot modes:

D Host boot

If host boot is selected, upon release of internal reset, the CPU is internally “stalled” while the remainder of

the device is released. During this period, an external host can initialize the CPU’s memory space as

necessary through the host interface, including internal configuration registers, such as those that control

the EMIF or other peripherals. Once the host is finished with all necessary initialization, it must set the

DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration

logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT

condition is not latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT

brings the CPU out of the “stalled” state only if the host boot process is selected. All memory may be written

to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is

out of the “stalled” state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.

D Emulation boot

Emulation boot mode is a variation of host boot. In this mode, it is not necessary for a host to load code or to

set DSPINT to release the CPU from the “stalled” state. Instead, the emulator will set DSPINT if it has not

been previously set so that the CPU can begin executing code from address 0. Prior to beginning execution,

the emulator sets a breakpoint at address 0. This prevents the execution of invalid code by halting the CPU

prior to executing the first instruction. Emulation boot is a good tool in the debug phase of development.

D EMIF boot (using default ROM timings)

Upon the release of internal reset, the 1K-Byte ROM code located in the beginning of CE1 is copied to

address 0 by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should

be stored in the endian format that the system is using. The boot process also lets you choose the width of

the ROM. In this case, the EMIF automatically assembles consecutive 8-bit bytes or 16-bit half-words to

form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a

single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is

released from the “stalled” state and start running from address 0.

absolute maximum ratings over operating case temperature range (unless otherwise noted)†

Supply voltage range, CVDD (see Note 2): (C6711C/C6711D only)

− 0.3 V to 1.8 V

. . . . . . . . . . . . . . . . . . . . .

(C6711/C6711B)

− 0.3 V to 2.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage range, DVDD (see Note 2)

−0.3 V to 4 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage ranges:

(C6711C/C6711D only)

−0.3 V to DVDD + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(C6711/C6711B)

−0.3 V to 4 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage ranges: (C6711C/C6711D only)

−0.3 V to DVDD + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(C6711/C6711B)

−0.3 V to 4 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating case temperature ranges, TC: (default)

0_C to 90_C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(A version) [C6711BGFNA and C6711CGDPA] −40_C to105_C

Storage temperature range, Tstg

−65_C to 150_C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 2: All voltage values are with respect to VSS.

TMS320C6711 Datasheet(PDF) 64 Page - Texas Instruments

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