TMS320C6711 datasheet(92/129 Pages) TI

92 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

RESET TIMING [C6711/11B]

timing requirements for reset† (see Figure 43)

NO.

–100

–150

UNIT

NO.

MIN

MAX

UNIT

Width of the RESET pulse (PLL stable)‡

10P

tw(RST)

Width of the RESET pulse (PLL needs to sync up)§

250

µs

tsu(HD)

Setup time, HD boot configuration bits valid before RESET high¶

th(HD)

Hold time, HD boot configuration bits valid after RESET high¶

† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

‡ This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4 when CLKIN and PLL are stable.

§ This parameter applies to CLKMODE x4 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL

circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During

that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.

¶ HD[4:3] are the boot configuration pins during device reset.

switching characteristics over recommended operating conditions during reset†#|| (see Figure 43)

NO.

PARAMETER

–100

–150

−250 (6711D)

UNIT

MIN

MAX

td(RSTL-ECKI)

Delay time, RESET low to ECLKIN synchronized internally

2P + 3E

3P + 4E

td(RSTH-ECKI)

Delay time, RESET high to ECLKIN synchronized internally

2P + 3E

3P + 4E

td(RSTL-EMIFZHZ) Delay time, RESET low to EMIF Z group high impedance

2P + 3E

td(RSTH-EMIFZV)

Delay time, RESET high to EMIF Z group valid

3P + 4E

td(RSTL-EMIFHIV) Delay time, RESET low to EMIF high group invalid

2P + 3E

td(RSTH-EMIFHV)

Delay time, RESET high to EMIF high group valid

3P + 4E

td(RSTL-EMIFLIV)

Delay time, RESET low to EMIF low group invalid

2P + 3E

td(RSTH-EMIFLV)

Delay time, RESET high to EMIF low group valid

3P + 4E

td(RSTL-HIGHIV)

Delay time, RESET low to high group invalid

td(RSTH-HIGHV)

Delay time, RESET high to high group valid

td(RSTL-ZHZ)

Delay time, RESET low to Z group high impedance

td(RSTH-ZV)

Delay time, RESET high to Z group valid

† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

# E = ECLKIN period in ns

|| EMIF Z group consists of:

EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE

EMIF high group consists of: HOLDA

EMIF low group consists of:

BUSREQ

High group consists of:

HRDY and HINT

Z group consists of:

HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1.

TMS320C6711 Datasheet(PDF) 92 Page - Texas Instruments

TMS320C6711 Datasheet(HTML) 92 Page - Texas Instruments

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