TMS320C6711 datasheet(94/129 Pages) TI

94 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

RESET TIMING [C6711C/11D]

timing requirements for reset†‡ (see Figure 44)

NO.

GDPA-167

−200

−250 (6711D)

UNIT

MIN

MAX

tw(RST)

Pulse duration, RESET

100

tsu(HD)

Setup time, HD boot configuration bits valid before RESET high§

th(HD)

Hold time, HD boot configuration bits valid after RESET high§

† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

‡ For the C6711C/C6711D device, the PLL is bypassed immediately after the device comes out of reset. The PLL Controller can be programmed

to change the PLL mode in software. For more detailed information on the PLL Controller, see the TMS320C6000 DSP Software-Programmable

Phase-Lock Loop (PLL) Controller Reference Guide

(literature number SPRU233).

§ The Boot and device configurations bits are latched asynchronously when RESET is transitioning high. The Boot and device configurations bits

consist of: HD[8, 4:3].

switching characteristics over recommended operating conditions during reset¶ (see Figure 44)

NO.

PARAMETER

GDPA-167

−200

−250 (6711D)

UNIT

MIN

MAX

td(RSTH-ZV)

Delay time, external RESET high to internal reset

high and all signal groups valid#||

CLKMODE0 = 1

512 x CLKIN

period

td(RSTL-ECKOL)

Delay time, RESET low to ECLKOUT low (6711C)

td(RSTL-ECKOL)

Delay time, RESET low to ECLKOUT high impedance (6711D)

td(RSTH-ECKOV)

Delay time, RESET high to ECLKOUT valid

td(RSTL-CKO2IV)

Delay time, RESET low to CLKOUT2 invalid (6711C)

td(RSTL-CKO2IV)

Delay time, RESET low to CLKOUT2 high impedance (6711D)

td(RSTH-CKO2V)

Delay time, RESET high to CLKOUT2 valid

td(RSTL-CKO3L)

Delay time, RESET low to CLKOUT3 low

td(RSTH-CKO3V)

Delay time, RESET high to CLKOUT3 valid

td(RSTL-EMIFZHZ)

Delay time, RESET low to EMIF Z group high impedance||

td(RSTL-EMIFLIV)

Delay time, RESET low to EMIF low group (BUSREQ) invalid||

td(RSTL-Z1HZ)

Delay time, RESET low to Z group 1 high impedance||

td(RSTL-Z2HZ)

Delay time, RESET low to Z group 2 high impedance||

¶ P = 1/CPU clock frequency in ns.

Note that while internal reset is asserted low, the CPU clock (SYSCLK1) period is equal to the input clock (CLKIN) period multiplied by 8. For

example, if the CLKIN period is 20 ns, then the CPU clock (SYSCLK1) period is 20 ns x 8 = 160 ns. Therefore, P = SYSCLK1 = 160 ns while

internal reset is asserted.

# The internal reset is stretched exactly 512 x CLKIN cycles if CLKIN is used (CLKMODE0 = 1). If the input clock (CLKIN) is not stable when RESET

is deasserted, the actual delay time may vary.

|| EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and

HOLDA

EMIF low group consists of: BUSREQ

Z group 1 consists of:

CLKR0, CLKR1, CLKX0, CLKX1, FSR0, FSR1, FSX0, FSX1, DX0, DX1, TOUT0, and TOUT1.

Z group 2 consists of:

All other HPI and GPIO signals

TMS320C6711 Datasheet(PDF) 94 Page - Texas Instruments

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