TMS320C6711 datasheet(48/129 Pages) TI

48 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

clock PLL [C6711/11B only] (continued)

CLKMODE0

PLL

PLLV

CLKIN

LOOP FILTER

PLLCLK

PLLMULT

CLKIN

Internal to

C6711/C6711B

CPU

CLOCK

3.3V

NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal.

B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.

Figure 9. External PLL Circuitry for x1 (Bypass) Mode Only [C6711/11B]

Table 30. C6711/C6711B PLL Component Selection

CLKMODE

CLKIN

RANGE

(MHz)

CPU CLOCK

FREQUENCY

(CLKOUT1)

RANGE (MHz)

CLKOUT2

RANGE

(MHz)

R1 [±1%]

(Ω)

C1 [±10%]

(nF)

C2 [±10%]

(pF)

TYPICAL

LOCK TIME

(µs)†

16.3−41.6

65−167

32.5−83

60.4

560

† Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the

typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.

TMS320C6711 Datasheet(PDF) 48 Page - Texas Instruments

TMS320C6711 Datasheet(HTML) 48 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL