TMS320C6711 datasheet(63/129 Pages) TI

63 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

EMIF big endian mode correctness [C6711D only]

The HD8 pin device endian mode (LENDIAN) selects the endian mode of operation (Little or Big Endian). For

the C6711C/11D device Little Endian is the default setting.

The C6711D HD12 pin (EMIF Big Endian Mode Correctness) [EMIFBE] enhancement allows the flexibility to

change the EMIF data placement on the EMIF bus.

When using the default setting of HD12 = 1 for the C6711D, the EMIF will present 8-bit and 16-bit data on the

ED[7:0] side of the bus if using Little Endian mode (HD8 = 1) and to the ED[31:24] side of the bus if using Big

Endian mode. Figure 16 shows the mapping of 16-bit and 8-bit C6711D devices with EMIF endianness

correction.

EMIF DATA LINES (PINS) WHERE DATA PRESENT

ED[31:24] (BE3)

ED[23:16] (BE2)

ED[15:8] (BE1)

ED[7:0] (BE0)

32-Bit Device in ??? Endianness Mode

16-Bit Device in Big Endianness Mode

16-Bit Device in Little Endianness Mode

8-Bit Device in Big

Endianness Mode

8-Bit Device in Little Endianness Mode

Figure 16. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 1) [C6711D Only]

When HD12 = 0 for the C6711D, enabling EMIF endianness correction, the EMIF will present 8-bit and 16-bit

data on the ED[7:0] side of the bus, regardless of the endianess mode (see Figure 17).

EMIF DATA LINES (PINS) WHERE DATA PRESENT

ED[31:24] (BE3)

ED[23:16] (BE2)

ED[15:8] (BE1)

ED[7:0] (BE0)

32-Bit Device in ??? Endianness Mode

16-Bit Device in Any Endianness Mode

8-Bit Device in Any Endianness Mode

Figure 17. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 0) [C6711D Only]

This new C6711D endianness correction functionality does not affect systems using the default value of

HD12=1.

This new feature does not affect systems operating in Little Endian mode.

bootmode

The C67x device resets using the active-low signal RESET and the internal reset signal (C6711C/C6711D;

for the C6711/C6711B device, the RESET signal is the same as the internal reset signal). While RESET is low,

the internal reset is also asserted and the device is held in reset and is initialized to the prescribed reset state.

Refer to reset timing for reset timing characteristics and states of device pins during reset. The release of the

internal reset signal (see the Reset Phase 3 discussion in the Reset Timing section of this data sheet) starts

the processor running with the prescribed device configuration and boot mode.

TMS320C6711 Datasheet(PDF) 63 Page - Texas Instruments

TMS320C6711 Datasheet(HTML) 63 Page - Texas Instruments

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