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TMS320C6711 Datasheet(PDF) 25 Page - Texas Instruments |
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TMS320C6711 Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 129 page  TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D FLOATING-POINT DIGITAL SIGNAL PROCESSORS SPRS088L − FEBRUARY 1999 − REVISED MAY 2004 25 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL PIN NO. TYPE† IPD/ DESCRIPTION SIGNAL NAME GFN GDP TYPE† IPD/ IPU‡ DESCRIPTION HOST-PORT INTERFACE (HPI) (CONTINUED) HD15 B14 B14 IPU Host-port data • Used for transfer of data, address, and control HD14 C14 C14 IPU • Used for transfer of data, address, and control • Also controls initialization of DSP modes at reset via pullup/pulldown resistors − Device Endian mode (HD8) HD13 A15 A15 IPU Device Endian mode (HD8) 0 – Big Endian 1 − Little Endian HD12 C15 C15 IPU EMIF Big Endian mode correctness (EMIFBE) (HD12) [C6711D only] 0 – The EMIF data will always be presented on the ED[7:0] side of the bus HD11 A16 A16 IPU 0 – The EMIF data will always be presented on the ED[7:0] side of the bus, regardless of the endianess mode (Little/Big Endian). 1 − In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will be HD10 B16 B16 IPU 1 In Little Endian mode (HD8 =1), the 8 bit or 16 bit EMIF data will be present on the ED[7:0] side of the bus. In Big Endian mode (HD8 =0), the 8-bit or 16-bit EMIF data will be present th ED[31 24] id f th b [d f lt] HD9 C16 C16 IPU g on the ED[31:24] side of the bus [default]. This enhancement is not supported on the C6711/11B/11C device HD8 B17 B17 I/O/Z IPU This enhancement is not supported on the C6711/11B/11C device. For proper C6711/11B/11C device operation, do not oppose the internal pullup (IPU) resistor on this pin. HD7 A18 A18 I/O/Z IPU resistor on this pin. This new functionality does not affect systems using the current default value of HD12 1 F d il d i f i h bi di d h HD6 C17 C17 IPU y yg HD12=1. For more detailed information on the big endian mode correctness, see the EMIF Big Endian Mode Correctness [C6711D Only] portion of this data sheet. HD5 B18 B18 IPU − Boot mode (HD[4:3]) 00 – CE1 width 32-bit, HPI boot/Emulation boot HD4 C19 C19 IPD 00 – CE1 width 32-bit, HPI boot/Emulation boot 01 − CE1 width 8-bit, Asynchronous external ROM boot with default timings (default mode) HD3 C20 C20 IPU () 10 − CE1 width 16-bit, Asynchronous external ROM boot with default timings 11 − CE1 width 32-bit, Asynchronous external ROM boot with default timings HD2 D18 D18 IPU Other HD pins [HD [15:9, 7:5, 2:0] (for 11/11B/11C) or HD [15:13, 11:9, 7:5, 2:0] (for 11D)] have pullups/pulldowns (IPUs/IPDs). For proper device operation of the HD1 D20 D20 IPU 11D)] have pullups/pulldowns (IPUs/IPDs). For proper device operation of the HD[15:9, 7, 1, 0] for 11/11B/11C or HD[14, 13, 11:9, 7, 1, 0] for 11D, do not oppose these pins with external IPUs/IPDs at reset; however, the HD[6, 5, 2] for 11/11B/11C HD0 E20 E20 IPU these pins with external IPUs/IPDs at reset; however, the HD[6, 5, 2] for 11/11B/11C or HD[15, 6, 5, 2] for 11D pins can be opposed and driven during reset. For more de- tails, see the Device Configurations section of this data sheet. HAS E18 E18 I IPU Host address strobe HCS F20 F20 I IPU Host chip select HDS1 E19 E19 I IPU Host data strobe 1 HDS2 F18 F18 I IPU Host data strobe 2 HRDY H19 H19 O IPD Host ready (from DSP to host) † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ For C6711/11B, IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) For C6711C/11D, IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-kΩ resistor (approximate) for the IPD or 18-kΩ resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be used to pull a signal to the opposite supply rail.] # To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. |
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