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TMS320C6711 Datasheet(PDF) 29 Page - Texas Instruments |
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TMS320C6711 Datasheet(HTML) 29 Page - Texas Instruments |
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29 / 129 page ![]() TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D FLOATING-POINT DIGITAL SIGNAL PROCESSORS SPRS088L − FEBRUARY 1999 − REVISED MAY 2004 29 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL PIN NO. TYPE† IPD/ DESCRIPTION SIGNAL NAME GFN GDP TYPE† IPD/ IPU‡ DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) (CONTINUED) DX1 L2 L2 O/Z IPU Transmit data FSR1 M3 M3 I/O/Z IPD Receive frame sync FSX1 L1 L1 I/O/Z IPD Transmit frame sync MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 K3 K3 I IPD External clock source (as opposed to internal) CLKR0 H3 H3 I/O/Z IPD Receive clock CLKX0 G3 G3 I/O/Z IPD Transmit clock DR0 J1 J1 I IPU Receive data DX0 H2 H2 O/Z IPU Transmit data FSR0 J3 J3 I/O/Z IPD Receive frame sync FSX0 H1 H1 I/O/Z IPD Transmit frame sync GENERAL-PURPOSE INPUT/OUTPUT (GPIO) MODULE [C6711C/C6711D ONLY] CLKOUT2/ GP[2] Y12 Y12 I/O/Z IPD Clock output at half of device speed [C6711/11B only] For the C6711C/11D device, the CLKOUT2 pin is multiplexed with the GP[2] pin. Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the clock generator) or this pin can be programmed as GP[2] (I/O/Z). When the CLKOUT2 pin is enabled, the CLK2EN bit in the EMIF global control register (GBLCTL) controls the CLKOUT2 pin (All devices). CLK2EN = 0: CLKOUT2 is disabled CLK2EN = 1: CLKOUT2 enabled to clock [default] GP[7](EXT_INT7) E3 E3 External interrupts [C6711/11B only] • Edge-driven P l it i d d tl l t d i th E t l I t t P l it R i t GP[6](EXT_INT6) D2 D2 I/O/Z IPU • Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]) GP[5](EXT_INT5) C1 C1 I/O/Z IPU General-purpose input/output pins (I/O/Z) which also function as external interrupts [C6711C/11D only] • Edge driven GP[4](EXT_INT4) C2 C2 • Edge-driven • Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]), in addition to the GPIO registers. RESERVED FOR TEST RSV C12 C12 IPU Reserved (leave unconnected, do not connect to power or ground). Only the C6711/11B devices have internal pullup (IPU) on this pin. On the C6711C/11D device, this pin does not have an IPU. RSV D12 D12 IPU Only the C6711/11B devices have internal pullups (IPUs). For the C6711/11B, the D12 pin is reserved (leave unconnected, do not connect to power or ground). On the C6711C/11D device, this pin does not have an IPU. For proper C6711C/11D device operation, the D12 pin must be externally pulled down with a 10-kΩ resistor. RSV A5 A5 IPU Reserved (leave unconnected, do not connect to power or ground) † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ For C6711/11B, IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) For C6711C/11D, IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-kΩ resistor (approximate) for the IPD or 18-kΩ resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be used to pull a signal to the opposite supply rail.] |
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