TMS320C6711 datasheet(47/129 Pages) TI

47 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

clock PLL [C6711/11B only]

All of the internal C6711/11B clocks are generated from a single source through the CLKIN pin. This source clock

either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or

bypasses the PLL to become the internal CPU clock.

To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 8

shows the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Figure 9 shows the

external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.

To minimize the clock jitter, a single clean power supply should power both the C6711/11B device and the

external clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum

CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and

output clocks

electricals section.

Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source

must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended

ranges of supply voltage and operating case temperature

table and the input and output clocks electricals

section). Table 29 lists some examples of compatible CLKIN external clock sources:

Table 29. Compatible CLKIN External Clock Sources [C6711/11B]

COMPATIBLE PARTS FOR

EXTERNAL CLOCK SOURCES (CLKIN)

PART NUMBER

MANUFACTURER

JITO-2

Fox Electronix

Oscillators

STA series, ST4100 series

SaRonix Corporation

Oscillators

SG-636

Epson America

342

Corning Frequency Control

PLL

ICS525-02

Integrated Circuit Systems

Available Multiply Factors

CLKMODE0

PLL Multiply

Factors

CPU Clock

Frequency

f(CPUCLOCK)

x1(BYPASS)

1 x f(CLKIN)

4 x f(CLKIN)

NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition,

place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the C6000 device as possible. For the best

performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or

components other than the ones shown.

B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,

and the EMI filter).

C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.

D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.

Figure 8. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode [C6711/11B]

CLKMODE0

PLL

PLLV

CLKIN

LOOP FILTER

PLLCLK

PLLMULT

CLKIN

Internal to

C6711/C6711B

CPU

CLOCK

3.3V

10 mF

0.1 mF

(For C1, C2, and R1 values, see Table 30.)

TMS320C6711 Datasheet(PDF) 47 Page - Texas Instruments

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