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TMS320C6711 Datasheet(PDF) 93 Page - Texas Instruments |
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TMS320C6711 Datasheet(HTML) 93 Page - Texas Instruments |
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93 / 129 page  TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D FLOATING-POINT DIGITAL SIGNAL PROCESSORS SPRS088L − FEBRUARY 1999 − REVISED MAY 2004 93 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 RESET TIMING [C6711/11B] (CONTINUED) 13 12 11 10 9 8 7 6 5 4 3 2 15 14 1 CLKOUT1 CLKOUT2 RESET ECLKIN† EMIF Z Group‡ EMIF High Group‡ EMIF Low Group‡ High Group‡ Z Group‡ HD[8, 4:3]§ † ECLKIN should be provided during reset in order to drive EMIF signals to the correct reset values. ECLKOUT continues to clock as long as ECLKIN is provided. ‡ EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE EMIF high group consists of: HOLDA EMIF low group consists of: BUSREQ High group consists of: HRDY and HINT Z group consists of: HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1. § HD[8, 4:3] are the endianness and boot configuration pins during device reset. Figure 43. Reset Timing [C6711/11B] |
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