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TMS320C6711 Datasheet(PDF) 112 Page - Texas Instruments |
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TMS320C6711 Datasheet(HTML) 112 Page - Texas Instruments |
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112 / 129 page  TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D FLOATING-POINT DIGITAL SIGNAL PROCESSORS SPRS088L − FEBRUARY 1999 − REVISED MAY 2004 112 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 52) [C6711C/C6711D] NO. PARAMETER 11CGDPA-167 11C−200 11DGDPA-167 11D−200 11D−250 UNIT NO. PARAMETER MASTER§ SLAVE MASTER§ SLAVE UNIT MIN MAX MIN MAX MIN MAX MIN MAX 1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶ T − 2 T + 3 T − 2 T + 3 ns 2 td(FXL-CKXH) Delay time, FSX low to CLKX high# L − 2 L + 3 L − 2 L + 3 ns 3 td(CKXH-DXV) Delay time, CLKX high to DX valid −3 4 6P + 2 10P + 17 −3 4 6P + 2 10P + 17 ns 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low L − 4 L + 3 L − 2 L + 3 ns 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 2P + 1.5 6P + 17 2P + 3 6P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 17 4P + 2 8P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 CLKX FSX DX DR Figure 52. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 |
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