TMS320VC5407 datasheet(39/110 Pages) TI

39 / 110 page

Functional Overview

November 2001 − Revised April 2004

SPRS007D

3.10 Clock Generator

The clock generator provides clocks to the 5407/5404 device, and consists of a phase-locked loop (PLL)

circuit. The clock generator requires a reference clock input, which can be provided from an external clock

source. The reference clock input is then divided by two (DIV mode) to generate clocks for the 5407/5404

device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference

clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU.

The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.

When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input

signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,

other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the

5407/5404 device.

This clock generator allows system designers to select the clock source. The sources that drive the clock

generator are:

•

A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins

of the 5407/5404 to enable the internal oscillator.

•

An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left

unconnected.

The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides

various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can

be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a

built-in software-programmable PLL can be configured in one of two clock modes:

•

PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios.

•

DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can

be completely disabled in order to minimize power dissipation.

The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode

that upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state

of the CLKMD1 − CLKMD3 pins. For more programming information, see the TMS320C54x DSP Reference

Set, Volume 1: CPU and Peripherals (literature number SPRU131). The CLKMD pin configured clock options

are shown in Table 3−8.

Table 3−8. Clock Mode Settings at Reset

CLKMD1

CLKMD2

CLKMD3

CLKMD RESET

VALUE

CLOCK MODE†

0000h

1/2 (PLL and oscillator disabled)

9007h

PLL x 10

4007h

PLL x 5

1007h

PLL x 2

F007h

PLL x 1

F000h

1/4 (PLL disabled)

0000h

1/2 (PLL disabled)

—

Reserved

† The external CLKMD1−CLKMD3 pins are sampled to determine the desired clock generation mode

while RS is low. Following reset, the clock generation mode can be reconfigured by writing to the internal

clock mode register in software.

TMS320VC5407 Datasheet(PDF) 39 Page - Texas Instruments

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